^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2004 Koninklijke Philips Electronics NV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Conversion to platform driver and DT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 14/04/2005 Initial version, colin.king@philips.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static void __iomem *versatile_pci_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static void __iomem *versatile_cfg_base[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PCI_IMAP(m) (versatile_pci_base + ((m) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_SMAP(m) (versatile_pci_base + 0x14 + ((m) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCI_SELFID (versatile_pci_base + 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define VP_PCI_DEVICE_ID 0x030010ee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VP_PCI_CLASS_ID 0x0b400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static u32 pci_slot_ignore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int __init versatile_pci_slot_ignore(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) while ((retval = get_option(&str, &slot))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if ((slot < 0) || (slot > 31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) pr_err("Illegal slot value: %d\n", slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) pci_slot_ignore |= (1 << slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __setup("pci_slot_ignore=", versatile_pci_slot_ignore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void __iomem *versatile_map_bus(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int devfn, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned int busnr = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (pci_slot_ignore & (1 << PCI_SLOT(devfn)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return versatile_cfg_base[1] + ((busnr << 16) | (devfn << 8) | offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct pci_ops pci_versatile_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .map_bus = versatile_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .read = pci_generic_config_read32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .write = pci_generic_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int versatile_pci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct resource_entry *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int i, myslot = -1, mem = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *local_pci_cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bridge = devm_pci_alloc_host_bridge(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) versatile_pci_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (IS_ERR(versatile_pci_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return PTR_ERR(versatile_pci_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) versatile_cfg_base[0] = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (IS_ERR(versatile_cfg_base[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return PTR_ERR(versatile_cfg_base[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) versatile_cfg_base[1] = devm_pci_remap_cfg_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (IS_ERR(versatile_cfg_base[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return PTR_ERR(versatile_cfg_base[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) resource_list_for_each_entry(entry, &bridge->windows) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (resource_type(entry->res) == IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) writel(entry->res->start >> 28, PCI_IMAP(mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel(__pa(PAGE_OFFSET) >> 28, PCI_SMAP(mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mem++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * We need to discover the PCI core first to configure itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * before the main PCI probing is performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) for (i = 0; i < 32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if ((readl(versatile_cfg_base[0] + (i << 11) + PCI_VENDOR_ID) == VP_PCI_DEVICE_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) (readl(versatile_cfg_base[0] + (i << 11) + PCI_CLASS_REVISION) == VP_PCI_CLASS_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) myslot = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (myslot == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dev_err(dev, "Cannot find PCI core!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Do not to map Versatile FPGA PCI device into memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pci_slot_ignore |= (1 << myslot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dev_info(dev, "PCI core found (slot %d)\n", myslot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel(myslot, PCI_SELFID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) local_pci_cfg_base = versatile_cfg_base[1] + (myslot << 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val = readl(local_pci_cfg_base + PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel(val, local_pci_cfg_base + PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel(__pa(PAGE_OFFSET), local_pci_cfg_base + PCI_BASE_ADDRESS_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * For many years the kernel and QEMU were symbiotically buggy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * in that they both assumed the same broken IRQ mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * QEMU therefore attempts to auto-detect old broken kernels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * so that they still work on newer QEMU as they did on old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * QEMU. Since we now use the correct (ie matching-hardware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * IRQ mapping we write a definitely different value to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * PCI_INTERRUPT_LINE register to tell QEMU that we expect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * real hardware behaviour and it need not be backwards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * compatible for us. This write is harmless on real hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pci_add_flags(PCI_REASSIGN_ALL_BUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bridge->ops = &pci_versatile_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return pci_host_probe(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct of_device_id versatile_pci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { .compatible = "arm,versatile-pci", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MODULE_DEVICE_TABLE(of, versatile_pci_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct platform_driver versatile_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .name = "versatile-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .of_match_table = versatile_pci_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .probe = versatile_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) module_platform_driver(versatile_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MODULE_DESCRIPTION("Versatile PCI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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