^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for V3 Semiconductor PCI Local Bus to PCI Bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on the code from arch/arm/mach-integrator/pci_v3.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999 ARM Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Contributors to the old driver include:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Russell King <linux@armlinux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * David A. Rusling <david.rusling@linaro.org> (uHAL, ARM Firmware suite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Rob Herring <robh@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Liviu Dudau <Liviu.Dudau@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Grant Likely <grant.likely@secretlab.ca>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Arnd Bergmann <arnd@arndb.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Bjorn Helgaas <bhelgaas@google.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define V3_PCI_VENDOR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define V3_PCI_DEVICE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define V3_PCI_CMD 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define V3_PCI_STAT 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define V3_PCI_CC_REV 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define V3_PCI_HDR_CFG 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define V3_PCI_IO_BASE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define V3_PCI_BASE0 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define V3_PCI_BASE1 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define V3_PCI_SUB_VENDOR 0x0000002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define V3_PCI_SUB_ID 0x0000002E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define V3_PCI_ROM 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define V3_PCI_BPARAM 0x0000003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define V3_PCI_MAP0 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define V3_PCI_MAP1 0x00000044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define V3_PCI_INT_STAT 0x00000048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define V3_PCI_INT_CFG 0x0000004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define V3_LB_BASE0 0x00000054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define V3_LB_BASE1 0x00000058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define V3_LB_MAP0 0x0000005E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define V3_LB_MAP1 0x00000062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define V3_LB_BASE2 0x00000064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define V3_LB_MAP2 0x00000066
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define V3_LB_SIZE 0x00000068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define V3_LB_IO_BASE 0x0000006E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define V3_FIFO_CFG 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define V3_FIFO_PRIORITY 0x00000072
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define V3_FIFO_STAT 0x00000074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define V3_LB_ISTAT 0x00000076
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define V3_LB_IMASK 0x00000077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define V3_SYSTEM 0x00000078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define V3_LB_CFG 0x0000007A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define V3_PCI_CFG 0x0000007C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define V3_DMA_PCI_ADR0 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define V3_DMA_PCI_ADR1 0x00000090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define V3_DMA_LOCAL_ADR0 0x00000084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define V3_DMA_LOCAL_ADR1 0x00000094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define V3_DMA_LENGTH0 0x00000088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define V3_DMA_LENGTH1 0x00000098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define V3_DMA_CSR0 0x0000008B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define V3_DMA_CSR1 0x0000009B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define V3_DMA_CTLB_ADR0 0x0000008C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define V3_DMA_CTLB_ADR1 0x0000009C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define V3_DMA_DELAY 0x000000E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define V3_MAIL_DATA 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define V3_PCI_MAIL_IEWR 0x000000D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define V3_PCI_MAIL_IERD 0x000000D2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define V3_LB_MAIL_IEWR 0x000000D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define V3_LB_MAIL_IERD 0x000000D6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define V3_MAIL_WR_STAT 0x000000D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define V3_MAIL_RD_STAT 0x000000DA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define V3_QBA_MAP 0x000000DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* PCI STATUS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define V3_PCI_STAT_PAR_ERR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define V3_PCI_STAT_SYS_ERR BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define V3_PCI_STAT_M_ABORT_ERR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define V3_PCI_STAT_T_ABORT_ERR BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* LB ISTAT bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define V3_LB_ISTAT_MAILBOX BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define V3_LB_ISTAT_PCI_RD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define V3_LB_ISTAT_PCI_WR BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define V3_LB_ISTAT_PCI_INT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define V3_LB_ISTAT_PCI_PERR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define V3_LB_ISTAT_I2O_QWR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define V3_LB_ISTAT_DMA1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define V3_LB_ISTAT_DMA0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* PCI COMMAND bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define V3_COMMAND_M_FBB_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define V3_COMMAND_M_SERR_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define V3_COMMAND_M_PAR_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define V3_COMMAND_M_MASTER_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define V3_COMMAND_M_MEM_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define V3_COMMAND_M_IO_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* SYSTEM bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define V3_SYSTEM_M_RST_OUT BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define V3_SYSTEM_M_LOCK BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define V3_SYSTEM_UNLOCK 0xa05f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* PCI CFG bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define V3_PCI_CFG_M_I2O_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define V3_PCI_CFG_M_IO_REG_DIS BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define V3_PCI_CFG_M_IO_DIS BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define V3_PCI_CFG_M_EN3V BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define V3_PCI_CFG_M_RETRY_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define V3_PCI_CFG_M_AD_LOW1 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define V3_PCI_CFG_M_AD_LOW0 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * This is the value applied to C/BE[3:1], with bit 0 always held 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * during DMA access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define V3_PCI_CFG_M_RTYPE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define V3_PCI_CFG_M_WTYPE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define V3_PCI_CFG_TYPE_DEFAULT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* PCI BASE bits (PCI -> Local Bus) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define V3_PCI_BASE_M_ADR_BASE 0xFFF00000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define V3_PCI_BASE_M_PREFETCH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define V3_PCI_BASE_M_TYPE (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define V3_PCI_BASE_M_IO BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* PCI MAP bits (PCI -> Local bus) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define V3_PCI_MAP_M_MAP_ADR 0xFFF00000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define V3_PCI_MAP_M_RD_POST_INH BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define V3_PCI_MAP_M_SWAP (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define V3_PCI_MAP_M_ADR_SIZE 0x000000F0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define V3_PCI_MAP_M_REG_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define V3_PCI_MAP_M_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* LB_BASE0,1 bits (Local bus -> PCI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define V3_LB_BASE_ADR_BASE 0xfff00000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define V3_LB_BASE_SWAP (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define V3_LB_BASE_ADR_SIZE (15 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define V3_LB_BASE_PREFETCH BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define V3_LB_BASE_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* LB_MAP0,1 bits (Local bus -> PCI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define V3_LB_MAP_MAP_ADR 0xfff0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define V3_LB_MAP_TYPE (7 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define V3_LB_MAP_AD_LOW_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define V3_LB_MAP_TYPE_IACK (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define V3_LB_MAP_TYPE_IO (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define V3_LB_MAP_TYPE_MEM (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define V3_LB_MAP_TYPE_CONFIG (5 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* LB_BASE2 bits (Local bus -> PCI IO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define V3_LB_BASE2_ADR_BASE 0xff00U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define V3_LB_BASE2_SWAP_AUTO (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define V3_LB_BASE2_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* LB_MAP2 bits (Local bus -> PCI IO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define V3_LB_MAP2_MAP_ADR 0xff00U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* FIFO priority bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define V3_FIFO_PRIO_LOCAL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define V3_FIFO_PRIO_LB_RD1_FLUSH_EOB BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define V3_FIFO_PRIO_LB_RD1_FLUSH_ANY (BIT(10)|BIT(11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define V3_FIFO_PRIO_LB_RD0_FLUSH_EOB BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define V3_FIFO_PRIO_LB_RD0_FLUSH_ANY (BIT(8)|BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define V3_FIFO_PRIO_PCI BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define V3_FIFO_PRIO_PCI_RD1_FLUSH_EOB BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define V3_FIFO_PRIO_PCI_RD1_FLUSH_ANY (BIT(2)|BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define V3_FIFO_PRIO_PCI_RD0_FLUSH_EOB BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define V3_FIFO_PRIO_PCI_RD0_FLUSH_ANY (BIT(0)|BIT(1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Local bus configuration bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define V3_LB_CFG_LB_TO_64_CYCLES 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define V3_LB_CFG_LB_TO_256_CYCLES BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define V3_LB_CFG_LB_TO_512_CYCLES BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define V3_LB_CFG_LB_TO_1024_CYCLES (BIT(13)|BIT(14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define V3_LB_CFG_LB_RST BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define V3_LB_CFG_LB_PPC_RDY BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define V3_LB_CFG_LB_LB_INT BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define V3_LB_CFG_LB_ERR_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define V3_LB_CFG_LB_RDY_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define V3_LB_CFG_LB_BE_IMODE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define V3_LB_CFG_LB_BE_OMODE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define V3_LB_CFG_LB_ENDIAN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define V3_LB_CFG_LB_PARK_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define V3_LB_CFG_LB_FBB_DIS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* ARM Integrator-specific extended control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define INTEGRATOR_SC_PCI_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define INTEGRATOR_SC_PCI_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define INTEGRATOR_SC_PCI_INTCLR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct v3_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void __iomem *config_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 config_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 non_pre_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 pre_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) phys_addr_t non_pre_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) phys_addr_t pre_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * The V3 PCI interface chip in Integrator provides several windows from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * local bus memory into the PCI memory areas. Unfortunately, there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * are not really enough windows for our usage, therefore we reuse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * one of the windows for access to PCI configuration space. On the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Integrator/AP, the memory map is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Local Bus Memory Usage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * 60000000 - 60FFFFFF PCI IO. 16M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * 61000000 - 61FFFFFF PCI Configuration. 16M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * There are three V3 windows, each described by a pair of V3 registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * Base0 and Base1 can be used for any type of PCI memory access. Base2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * can be used either for PCI I/O or for I20 accesses. By default, uHAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * uses this only for PCI IO space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Normally these spaces are mapped using the following base registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Usage Local Bus Memory Base/Map registers used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Cfg 61000000 - 61FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * This means that I20 and PCI configuration space accesses will fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * When PCI configuration accesses are needed (via the uHAL PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * configuration space primitives) we must remap the spaces as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Usage Local Bus Memory Base/Map registers used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * To make this work, the code depends on overlapping windows working.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * The V3 chip translates an address by checking its range within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * each of the BASE/MAP pairs in turn (in ascending register number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * order). It will use the first matching pair. So, for example,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * if the same address is mapped by both LB_BASE0/LB_MAP0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * LB_BASE1/LB_MAP1, the V3 will use the translation from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * LB_BASE0/LB_MAP0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * To allow PCI Configuration space access, the code enlarges the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * be remapped for use by configuration cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * At the end of the PCI Configuration space accesses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * reveal the now restored LB_BASE1/LB_MAP1 window.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * NOTE: We do not set up I2O mapping. I suspect that this is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * for an intelligent (target) device. Using I2O disables most of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * the mappings into PCI memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void __iomem *v3_map_bus(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int devfn, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct v3_pci *v3 = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int address, mapaddress, busnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) busnr = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (busnr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int slot = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * local bus segment so need a type 0 config cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * build the PCI configuration "address" with one-hot in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * A31-A11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * mapaddress:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * 3:1 = config cycle (101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * 0 = PCI A1 & A0 are 0 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) address = PCI_FUNC(devfn) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mapaddress = V3_LB_MAP_TYPE_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (slot > 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * high order bits are handled by the MAP register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) mapaddress |= BIT(slot - 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * low order bits handled directly in the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) address |= BIT(slot + 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * not the local bus segment so need a type 1 config cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * address:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * 23:16 = bus number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * 15:11 = slot number (7:3 of devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * 10:8 = func number (2:0 of devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * mapaddress:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * 3:1 = config cycle (101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * 0 = PCI A1 & A0 from host bus (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) address = (busnr << 16) | (devfn << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Set up base0 to see all 512Mbytes of memory space (not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * prefetchable), this frees up base1 for re-use by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * configuration memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) writel(v3_addr_to_lb_base(v3->non_pre_mem) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) v3->base + V3_LB_BASE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * Set up base1/map1 to point into configuration space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * The config mem is always 16MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) writel(v3_addr_to_lb_base(v3->config_mem) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) v3->base + V3_LB_BASE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) writew(mapaddress, v3->base + V3_LB_MAP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return v3->config_base + address + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void v3_unmap_bus(struct v3_pci *v3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Reassign base1 for use by prefetchable PCI memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) writel(v3_addr_to_lb_base(v3->pre_mem) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) V3_LB_BASE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) v3->base + V3_LB_BASE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) V3_LB_MAP_TYPE_MEM, /* was V3_LB_MAP_TYPE_MEM_MULTIPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) v3->base + V3_LB_MAP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) writel(v3_addr_to_lb_base(v3->non_pre_mem) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) v3->base + V3_LB_BASE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int v3_pci_read_config(struct pci_bus *bus, unsigned int fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int config, int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct v3_pci *v3 = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_dbg(&bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "[read] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PCI_SLOT(fn), PCI_FUNC(fn), config, size, *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = pci_generic_config_read(bus, fn, config, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) v3_unmap_bus(v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int v3_pci_write_config(struct pci_bus *bus, unsigned int fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int config, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct v3_pci *v3 = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_dbg(&bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "[write] slt: %.2d, fnc: %d, cnf: 0x%.2X, val (%d bytes): 0x%.8X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PCI_SLOT(fn), PCI_FUNC(fn), config, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = pci_generic_config_write(bus, fn, config, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) v3_unmap_bus(v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct pci_ops v3_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .map_bus = v3_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .read = v3_pci_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .write = v3_pci_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static irqreturn_t v3_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct v3_pci *v3 = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct device *dev = v3->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) status = readw(v3->base + V3_PCI_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (status & V3_PCI_STAT_PAR_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(dev, "parity error interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (status & V3_PCI_STAT_SYS_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_err(dev, "system error interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (status & V3_PCI_STAT_M_ABORT_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(dev, "master abort error interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (status & V3_PCI_STAT_T_ABORT_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(dev, "target abort error interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) writew(status, v3->base + V3_PCI_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) status = readb(v3->base + V3_LB_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (status & V3_LB_ISTAT_MAILBOX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_info(dev, "PCI mailbox interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (status & V3_LB_ISTAT_PCI_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev_err(dev, "PCI target LB->PCI READ abort interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (status & V3_LB_ISTAT_PCI_WR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(dev, "PCI target LB->PCI WRITE abort interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (status & V3_LB_ISTAT_PCI_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_info(dev, "PCI pin interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (status & V3_LB_ISTAT_PCI_PERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(dev, "PCI parity error interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (status & V3_LB_ISTAT_I2O_QWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_info(dev, "I2O inbound post queue interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (status & V3_LB_ISTAT_DMA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_info(dev, "DMA channel 1 interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (status & V3_LB_ISTAT_DMA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_info(dev, "DMA channel 0 interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Clear all possible interrupts on the local bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writeb(0, v3->base + V3_LB_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (v3->map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) INTEGRATOR_SC_PCI_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) INTEGRATOR_SC_PCI_INTCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int v3_integrator_init(struct v3_pci *v3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) v3->map =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) syscon_regmap_lookup_by_compatible("arm,integrator-ap-syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (IS_ERR(v3->map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_err(v3->dev, "no syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) regmap_read(v3->map, INTEGRATOR_SC_PCI_OFFSET, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Take the PCI bridge out of reset, clear IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) regmap_write(v3->map, INTEGRATOR_SC_PCI_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) INTEGRATOR_SC_PCI_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) INTEGRATOR_SC_PCI_INTCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!(val & INTEGRATOR_SC_PCI_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* If we were in reset we need to sleep a bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) msleep(230);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Set the physical base for the controller itself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) writel(0x6200, v3->base + V3_LB_IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Wait for the mailbox to settle after reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) writeb(0xaa, v3->base + V3_MAIL_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) writeb(0x55, v3->base + V3_MAIL_DATA + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) } while (readb(v3->base + V3_MAIL_DATA) != 0xaa &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) readb(v3->base + V3_MAIL_DATA) != 0x55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_info(v3->dev, "initialized PCI V3 Integrator/AP integration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int v3_pci_setup_resource(struct v3_pci *v3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct pci_host_bridge *host,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct resource_entry *win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct device *dev = v3->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct resource *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) switch (resource_type(win->res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case IORESOURCE_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) io = win->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Setup window 2 - PCI I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) writel(v3_addr_to_lb_base2(pci_pio_to_address(io->start)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) V3_LB_BASE2_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) v3->base + V3_LB_BASE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) writew(v3_addr_to_lb_map2(io->start - win->offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) v3->base + V3_LB_MAP2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case IORESOURCE_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mem = win->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (mem->flags & IORESOURCE_PREFETCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mem->name = "V3 PCI PRE-MEM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) v3->pre_mem = mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) v3->pre_bus_addr = mem->start - win->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_dbg(dev, "PREFETCHABLE MEM window %pR, bus addr %pap\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) mem, &v3->pre_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (resource_size(mem) != SZ_256M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev_err(dev, "prefetchable memory range is not 256MB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (v3->non_pre_mem &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) (mem->start != v3->non_pre_mem + SZ_256M)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) "prefetchable memory is not adjacent to non-prefetchable memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Setup window 1 - PCI prefetchable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) writel(v3_addr_to_lb_base(v3->pre_mem) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) V3_LB_BASE_ADR_SIZE_256MB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) V3_LB_BASE_PREFETCH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) V3_LB_BASE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) v3->base + V3_LB_BASE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) writew(v3_addr_to_lb_map(v3->pre_bus_addr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) V3_LB_MAP_TYPE_MEM, /* Was V3_LB_MAP_TYPE_MEM_MULTIPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) v3->base + V3_LB_MAP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mem->name = "V3 PCI NON-PRE-MEM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) v3->non_pre_mem = mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) v3->non_pre_bus_addr = mem->start - win->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev_dbg(dev, "NON-PREFETCHABLE MEM window %pR, bus addr %pap\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mem, &v3->non_pre_bus_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (resource_size(mem) != SZ_256M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) "non-prefetchable memory range is not 256MB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Setup window 0 - PCI non-prefetchable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) writel(v3_addr_to_lb_base(v3->non_pre_mem) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) V3_LB_BASE_ADR_SIZE_256MB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) V3_LB_BASE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) v3->base + V3_LB_BASE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) writew(v3_addr_to_lb_map(v3->non_pre_bus_addr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) V3_LB_MAP_TYPE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) v3->base + V3_LB_MAP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case IORESOURCE_BUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_info(dev, "Unknown resource type %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) resource_type(win->res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int v3_get_dma_range_config(struct v3_pci *v3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct resource_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u32 *pci_base, u32 *pci_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct device *dev = v3->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u64 cpu_addr = entry->res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) u64 cpu_end = entry->res->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u64 pci_end = cpu_end - entry->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u64 pci_addr = entry->res->start - entry->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (pci_addr & ~V3_PCI_BASE_M_ADR_BASE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_err(dev, "illegal range, only PCI bits 31..20 allowed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) val = ((u32)pci_addr) & V3_PCI_BASE_M_ADR_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) *pci_base = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_err(dev, "illegal range, only CPU bits 31..20 allowed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) val = ((u32)cpu_addr) & V3_PCI_MAP_M_MAP_ADR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) switch (resource_size(entry->res)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case SZ_1M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) val |= V3_LB_BASE_ADR_SIZE_1MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case SZ_2M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) val |= V3_LB_BASE_ADR_SIZE_2MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case SZ_4M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) val |= V3_LB_BASE_ADR_SIZE_4MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) case SZ_8M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) val |= V3_LB_BASE_ADR_SIZE_8MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) case SZ_16M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) val |= V3_LB_BASE_ADR_SIZE_16MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case SZ_32M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) val |= V3_LB_BASE_ADR_SIZE_32MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case SZ_64M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) val |= V3_LB_BASE_ADR_SIZE_64MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case SZ_128M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) val |= V3_LB_BASE_ADR_SIZE_128MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case SZ_256M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) val |= V3_LB_BASE_ADR_SIZE_256MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case SZ_512M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) val |= V3_LB_BASE_ADR_SIZE_512MB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case SZ_1G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) val |= V3_LB_BASE_ADR_SIZE_1GB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case SZ_2G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) val |= V3_LB_BASE_ADR_SIZE_2GB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dev_err(v3->dev, "illegal dma memory chunk size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) val |= V3_PCI_MAP_M_REG_EN | V3_PCI_MAP_M_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) *pci_map = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) "DMA MEM CPU: 0x%016llx -> 0x%016llx => "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) cpu_addr, cpu_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pci_addr, pci_end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) *pci_base, *pci_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct pci_host_bridge *bridge = pci_host_bridge_from_priv(v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct device *dev = v3->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct resource_entry *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) resource_list_for_each_entry(entry, &bridge->dma_ranges) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u32 pci_base, pci_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ret = v3_get_dma_range_config(v3, entry, &pci_base, &pci_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) writel(pci_base, v3->base + V3_PCI_BASE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) writel(pci_map, v3->base + V3_PCI_MAP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) } else if (i == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) writel(pci_base, v3->base + V3_PCI_BASE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) writel(pci_map, v3->base + V3_PCI_MAP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) dev_err(dev, "too many ranges, only two supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_err(dev, "range %d ignored\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int v3_pci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct resource *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct resource_entry *win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct v3_pci *v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct pci_host_bridge *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) host = devm_pci_alloc_host_bridge(dev, sizeof(*v3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (!host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) host->ops = &v3_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) v3 = pci_host_bridge_priv(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) host->sysdata = v3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) v3->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* Get and enable host clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_err(dev, "clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_err(dev, "unable to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) v3->base = devm_ioremap_resource(dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (IS_ERR(v3->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return PTR_ERR(v3->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * The hardware has a register with the physical base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * of the V3 controller itself, verify that this is the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * as the physical memory we've remapped it from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (readl(v3->base + V3_LB_IO_BASE) != (regs->start >> 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) dev_err(dev, "V3_LB_IO_BASE = %08x but device is @%pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) readl(v3->base + V3_LB_IO_BASE), regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Configuration space is 16MB directly mapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (resource_size(regs) != SZ_16M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev_err(dev, "config mem is not 16MB!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) v3->config_mem = regs->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) v3->config_base = devm_ioremap_resource(dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (IS_ERR(v3->config_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return PTR_ERR(v3->config_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* Get and request error IRQ resource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ret = devm_request_irq(dev, irq, v3_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "PCIv3 error", v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "unable to request PCIv3 error IRQ %d (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * Unlock V3 registers, but only if they were previously locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (readw(v3->base + V3_SYSTEM) & V3_SYSTEM_M_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) writew(V3_SYSTEM_UNLOCK, v3->base + V3_SYSTEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Disable all slave access while we set up the windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) val = readw(v3->base + V3_PCI_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) writew(val, v3->base + V3_PCI_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Put the PCI bus into reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) val = readw(v3->base + V3_SYSTEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) val &= ~V3_SYSTEM_M_RST_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) writew(val, v3->base + V3_SYSTEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Retry until we're ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) val = readw(v3->base + V3_PCI_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) val |= V3_PCI_CFG_M_RETRY_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) writew(val, v3->base + V3_PCI_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Set up the local bus protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) val = readw(v3->base + V3_LB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) val |= V3_LB_CFG_LB_BE_IMODE; /* Byte enable input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) val |= V3_LB_CFG_LB_BE_OMODE; /* Byte enable output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) val &= ~V3_LB_CFG_LB_ENDIAN; /* Little endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) val &= ~V3_LB_CFG_LB_PPC_RDY; /* TODO: when using on PPC403Gx, set to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) writew(val, v3->base + V3_LB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* Enable the PCI bus master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) val = readw(v3->base + V3_PCI_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) val |= PCI_COMMAND_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) writew(val, v3->base + V3_PCI_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Get the I/O and memory ranges from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) resource_list_for_each_entry(win, &host->windows) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = v3_pci_setup_resource(v3, host, win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dev_err(dev, "error setting up resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = v3_pci_parse_map_dma_ranges(v3, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * Disable PCI to host IO cycles, enable I/O buffers @3.3V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * set AD_LOW0 to 1 if one of the LB_MAP registers choose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * to use this (should be unused).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) writel(0x00000000, v3->base + V3_PCI_IO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) val = V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) V3_PCI_CFG_M_EN3V | V3_PCI_CFG_M_AD_LOW0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * DMA read and write from PCI bus commands types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_RTYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) val |= V3_PCI_CFG_TYPE_DEFAULT << V3_PCI_CFG_M_WTYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) writew(val, v3->base + V3_PCI_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * Set the V3 FIFO such that writes have higher priority than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * reads, and local bus write causes local bus read fifo flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * on aperture 1. Same for PCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) writew(V3_FIFO_PRIO_LB_RD1_FLUSH_AP1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) V3_FIFO_PRIO_LB_RD0_FLUSH_AP1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) V3_FIFO_PRIO_PCI_RD1_FLUSH_AP1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) V3_FIFO_PRIO_PCI_RD0_FLUSH_AP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) v3->base + V3_FIFO_PRIORITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * Clear any error interrupts, and enable parity and write error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) writeb(0, v3->base + V3_LB_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) val = readw(v3->base + V3_LB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) val |= V3_LB_CFG_LB_LB_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) writew(val, v3->base + V3_LB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) writeb(V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) v3->base + V3_LB_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Special Integrator initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (of_device_is_compatible(np, "arm,integrator-ap-pci")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret = v3_integrator_init(v3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Post-init: enable PCI memory and invalidate (master already on) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) val = readw(v3->base + V3_PCI_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) val |= PCI_COMMAND_MEMORY | PCI_COMMAND_INVALIDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) writew(val, v3->base + V3_PCI_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* Clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) writeb(0, v3->base + V3_LB_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Read or write errors and parity errors cause interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) writeb(V3_LB_ISTAT_PCI_RD | V3_LB_ISTAT_PCI_WR | V3_LB_ISTAT_PCI_PERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) v3->base + V3_LB_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Take the PCI bus out of reset so devices can initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) val = readw(v3->base + V3_SYSTEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) val |= V3_SYSTEM_M_RST_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) writew(val, v3->base + V3_SYSTEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * Re-lock the system register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) val = readw(v3->base + V3_SYSTEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) val |= V3_SYSTEM_M_LOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) writew(val, v3->base + V3_SYSTEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return pci_host_probe(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static const struct of_device_id v3_pci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) .compatible = "v3,v360epc-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static struct platform_driver v3_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .name = "pci-v3-semi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .of_match_table = of_match_ptr(v3_pci_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .probe = v3_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) builtin_platform_driver(v3_pci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags