^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 - 2016 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci-acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci-ecam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #if defined(CONFIG_PCI_HOST_THUNDER_PEM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PEM_CFG_WR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PEM_CFG_RD 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct thunder_pem_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 ea_entry[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __iomem *pem_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u64 read_val, tmp_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct pci_config_window *cfg = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (devfn != 0 || where >= 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * 32-bit accesses only. Write the address to the low order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * bits of PEM_CFG_RD, then trigger the read by reading back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * The config data lands in the upper 32-bits of PEM_CFG_RD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) read_val = where & ~3ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) read_val >>= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * The config space contains some garbage, fix it up. Also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * synthesize an EA capability for the BAR used by MSI-X.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) switch (where & ~3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) case 0x40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) read_val &= 0xffff00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) read_val |= 0x00007000; /* Skip MSI CAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) case 0x70: /* Express Cap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Change PME interrupt to vector 2 on T88 where it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * reads as 0, else leave it alone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!(read_val & (0x1f << 25)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) read_val |= (2u << 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case 0xb0: /* MSI-X Cap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* TableSize=2 or 4, Next Cap is EA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) read_val &= 0xc00000ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * If Express Cap(0x70) raw PME vector reads as 0 we are on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * T88 and TableSize is reported as 4, else TableSize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * is 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) tmp_val >>= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!(tmp_val & (0x1f << 25)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) read_val |= 0x0003bc00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) read_val |= 0x0001bc00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case 0xb4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Table offset=0, BIR=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) read_val = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case 0xb8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* BPA offset=0xf0000, BIR=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) read_val = 0x000f0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case 0xbc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* EA, 1 entry, no next Cap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) read_val = 0x00010014;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case 0xc0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* DW2 for type-1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) read_val = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case 0xc4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) read_val = 0x80ff0003;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case 0xc8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) read_val = pem_pci->ea_entry[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case 0xcc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) read_val = pem_pci->ea_entry[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case 0xd0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) read_val = pem_pci->ea_entry[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) read_val >>= (8 * (where & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) read_val &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) read_val &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *val = read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pci_config_window *cfg = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (bus->number < cfg->busr.start ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bus->number > cfg->busr.end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * The first device on the bus is the PEM PCIe bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Special case its config access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (bus->number == cfg->busr.start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return thunder_pem_bridge_read(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return pci_generic_config_read(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Some of the w1c_bits below also include read-only or non-writable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * reserved bits, this makes the code simpler and is OK as the bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * are not affected by writing zeros to them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 w1c_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) switch (where_aligned) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case 0x04: /* Command/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case 0x1c: /* Base and I/O Limit/Secondary Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) w1c_bits = 0xff000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case 0x44: /* Power Management Control and Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) w1c_bits = 0xfffffe00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case 0x78: /* Device Control/Device Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case 0x80: /* Link Control/Link Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case 0x88: /* Slot Control/Slot Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case 0x90: /* Root Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case 0xa0: /* Link Control 2 Registers/Link Status 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) w1c_bits = 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case 0x104: /* Uncorrectable Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case 0x110: /* Correctable Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case 0x130: /* Error Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case 0x160: /* Link Control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) w1c_bits = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return w1c_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Some bits must be written to one so they appear to be read-only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 w1_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) switch (where_aligned) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Force 32-bit I/O addressing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) w1_bits = 0x0101;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Force 64-bit addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) w1_bits = 0x00010001;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) w1_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return w1_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct pci_config_window *cfg = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u64 write_val, read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u64 where_aligned = where & ~3ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (devfn != 0 || where >= 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * 32-bit accesses only. If the write is for a size smaller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * than 32-bits, we must first read the 32-bit value and merge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * in the desired bits and then write the whole 32-bits back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) read_val >>= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mask = ~(0xff << (8 * (where & 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) read_val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val = (val & 0xff) << (8 * (where & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) val |= (u32)read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) read_val >>= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mask = ~(0xffff << (8 * (where & 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) read_val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) val = (val & 0xffff) << (8 * (where & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val |= (u32)read_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * By expanding the write width to 32 bits, we may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * inadvertently hit some W1C bits that were not intended to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * be written. Calculate the mask that must be applied to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * data to be written to avoid these cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (w1c_bits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mask &= w1c_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Some bits must be read-only with value of one. Since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * access method allows these to be cleared if a zero is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * written, force them to one before writing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) val |= thunder_pem_bridge_w1_bits(where_aligned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Low order bits are the config address, the high order 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * bits are the data to be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) write_val = (((u64)val) << 32) | where_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct pci_config_window *cfg = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (bus->number < cfg->busr.start ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bus->number > cfg->busr.end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * The first device on the bus is the PEM PCIe bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Special case its config access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (bus->number == cfg->busr.start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return thunder_pem_bridge_write(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return pci_generic_config_write(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct resource *res_pem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct thunder_pem_pci *pem_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) resource_size_t bar4_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!pem_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!pem_pci->pem_reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * The MSI-X BAR for the PEM and AER interrupts is located at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * a fixed offset from the PEM register base. Generate a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * fragment of the synthesized Enhanced Allocation capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * structure here for the BAR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) bar4_start = res_pem->start + 0xf00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pem_pci->ea_entry[0] = lower_32_bits(bar4_start) | 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pem_pci->ea_entry[1] = lower_32_bits(res_pem->end - bar4_start) & ~3u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pem_pci->ea_entry[2] = upper_32_bits(bar4_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) cfg->priv = pem_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PEM_RES_BASE 0x87e0c0000000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PEM_NODE_MASK GENMASK_ULL(45, 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PEM_INDX_MASK GENMASK_ULL(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PEM_MIN_DOM_IN_NODE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PEM_MAX_DOM_IN_NODE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void thunder_pem_reserve_range(struct device *dev, int seg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct resource *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) resource_size_t start = r->start, end = r->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const char *regionid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) regionid = kasprintf(GFP_KERNEL, "PEM RC:%d", seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!regionid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) res = request_mem_region(start, end - start + 1, regionid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) res->flags &= ~IORESOURCE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) kfree(regionid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_info(dev, "%pR %s reserved\n", r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) res ? "has been" : "could not be");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void thunder_pem_legacy_fw(struct acpi_pci_root *root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct resource *res_pem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int node = acpi_get_node(root->device->handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (node == NUMA_NO_NODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) node = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) index = root->segment - PEM_MIN_DOM_IN_NODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) index -= node * PEM_MAX_DOM_IN_NODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) res_pem->start = PEM_RES_BASE | FIELD_PREP(PEM_NODE_MASK, node) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) FIELD_PREP(PEM_INDX_MASK, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) res_pem->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int thunder_pem_acpi_init(struct pci_config_window *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct device *dev = cfg->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct acpi_device *adev = to_acpi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct acpi_pci_root *root = acpi_driver_data(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct resource *res_pem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) res_pem = devm_kzalloc(&adev->dev, sizeof(*res_pem), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!res_pem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = acpi_get_rc_resources(dev, "CAVA02B", root->segment, res_pem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * If we fail to gather resources it means that we run with old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * FW where we need to calculate PEM-specific resources manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) thunder_pem_legacy_fw(root, res_pem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * Reserve 64K size PEM specific resources. The full 16M range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * size is required for thunder_pem_init() call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) res_pem->end = res_pem->start + SZ_64K - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) thunder_pem_reserve_range(dev, root->segment, res_pem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) res_pem->end = res_pem->start + SZ_16M - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Reserve PCI configuration space as well. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) thunder_pem_reserve_range(dev, root->segment, &cfg->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return thunder_pem_init(dev, cfg, res_pem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) const struct pci_ecam_ops thunder_pem_ecam_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .bus_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .init = thunder_pem_acpi_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .map_bus = pci_ecam_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .read = thunder_pem_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .write = thunder_pem_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #ifdef CONFIG_PCI_HOST_THUNDER_PEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int thunder_pem_platform_init(struct pci_config_window *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct device *dev = cfg->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct resource *res_pem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * The second register range is the PEM bridge to the PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * bus. It has a different config access method than those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * devices behind the bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!res_pem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_err(dev, "missing \"reg[1]\"property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return thunder_pem_init(dev, cfg, res_pem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct pci_ecam_ops pci_thunder_pem_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .bus_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .init = thunder_pem_platform_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .map_bus = pci_ecam_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .read = thunder_pem_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .write = thunder_pem_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct of_device_id thunder_pem_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .compatible = "cavium,pci-host-thunder-pem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .data = &pci_thunder_pem_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct platform_driver thunder_pem_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .of_match_table = thunder_pem_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .probe = pci_host_common_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) builtin_platform_driver(thunder_pem_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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