^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015, 2016 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci-ecam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #if defined(CONFIG_PCI_HOST_THUNDER_ECAM) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static void set_val(u32 v, int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) int shift = (where & 3) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) pr_debug("set_val %04x: %08x\n", (unsigned)(where & ~3), v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) v >>= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) v &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) v &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *val = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int handle_ea_bar(u32 e0, int bar, struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int devfn, int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Entries are 16-byte aligned; bits[2,3] select word in entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int where_a = where & 0xc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (where_a == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) set_val(e0, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (where_a == 0x4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) v = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) v &= ~0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) v |= 2; /* EA entry-1. Base-L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (where_a == 0x8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 barl_orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 barl_rb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) barl_orig = readl(addr + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writel(0xffffffff, addr + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) barl_rb = readl(addr + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) writel(barl_orig, addr + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* zeros in unsettable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) v = ~barl_rb & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) v |= 0xc; /* EA entry-2. Offset-L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (where_a == 0xc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) addr = bus->ops->map_bus(bus, devfn, bar + 4); /* BAR 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) v = readl(addr); /* EA entry-3. Base-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int thunder_ecam_p2_config_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct pci_config_window *cfg = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int where_a = where & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 node_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* EA Base[63:32] may be missing some bits ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) switch (where_a) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case 0xa8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case 0xbc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case 0xd0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case 0xe4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return pci_generic_config_read(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) addr = bus->ops->map_bus(bus, devfn, where_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) v = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Bit 44 of the 64-bit Base must match the same bit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * the config space access window. Since we are working with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * the high-order 32 bits, shift everything down by 32 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) node_bits = upper_32_bits(cfg->res.start) & (1 << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) v |= node_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 vendor_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 class_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int cfg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int where_a = where & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) addr = bus->ops->map_bus(bus, devfn, 0xc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) v = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Check for non type-00 header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) cfg_type = (v >> 16) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) addr = bus->ops->map_bus(bus, devfn, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) class_rev = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (class_rev == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) goto no_emulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if ((class_rev & 0xff) >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Pass-2 handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (cfg_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) goto no_emulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return thunder_ecam_p2_config_read(bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * All BARs have fixed addresses specified by the EA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * capability; they must return zero on read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (cfg_type == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ((where >= 0x10 && where < 0x2c) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) (where >= 0x1a4 && where < 0x1bc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* BAR or SR-IOV BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) addr = bus->ops->map_bus(bus, devfn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) vendor_device = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (vendor_device == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) goto no_emulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pr_debug("%04x:%04x - Fix pass#: %08x, where: %03x, devfn: %03x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) vendor_device & 0xffff, vendor_device >> 16, class_rev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) (unsigned) where, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Check for non type-00 header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (cfg_type == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bool has_msix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bool is_nic = (vendor_device == 0xa01e177d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bool is_tns = (vendor_device == 0xa01f177d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) addr = bus->ops->map_bus(bus, devfn, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* E_CAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) v = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) has_msix = (v & 0xff00) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (!has_msix && where_a == 0x70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) v |= 0xbc00; /* next capability is EA at 0xbc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (where_a == 0xb0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) addr = bus->ops->map_bus(bus, devfn, where_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) v = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (v & 0xff00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pr_err("Bad MSIX cap header: %08x\n", v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) v |= 0xbc00; /* next capability is EA at 0xbc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (where_a == 0xbc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (is_nic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) v = 0x40014; /* EA last in chain, 4 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) else if (is_tns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) v = 0x30014; /* EA last in chain, 3 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) else if (has_msix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) v = 0x20014; /* EA last in chain, 2 entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) v = 0x10014; /* EA last in chain, 1 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (where_a >= 0xc0 && where_a < 0xd0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* EA entry-0. PP=0, BAR0 Size:3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return handle_ea_bar(0x80ff0003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0x10, bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (where_a >= 0xd0 && where_a < 0xe0 && has_msix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* EA entry-1. PP=0, BAR4 Size:3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return handle_ea_bar(0x80ff0043,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 0x20, bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (where_a >= 0xe0 && where_a < 0xf0 && is_tns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* EA entry-2. PP=0, BAR2, Size:3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return handle_ea_bar(0x80ff0023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x18, bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (where_a >= 0xe0 && where_a < 0xf0 && is_nic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* EA entry-2. PP=4, VF_BAR0 (9), Size:3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return handle_ea_bar(0x80ff0493,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 0x1a4, bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (where_a >= 0xf0 && where_a < 0x100 && is_nic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* EA entry-3. PP=4, VF_BAR4 (d), Size:3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return handle_ea_bar(0x80ff04d3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0x1b4, bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } else if (cfg_type == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) bool is_rsl_bridge = devfn == 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) bool is_rad_bridge = devfn == 0xa0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) bool is_zip_bridge = devfn == 0xa8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) bool is_dfa_bridge = devfn == 0xb0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) bool is_nic_bridge = devfn == 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (where_a == 0x70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) addr = bus->ops->map_bus(bus, devfn, where_a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) v = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (v & 0xff00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pr_err("Bad PCIe cap header: %08x\n", v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) v |= 0xbc00; /* next capability is EA at 0xbc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (where_a == 0xbc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (is_nic_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) v = 0x10014; /* EA last in chain, 1 entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) v = 0x00014; /* EA last in chain, no entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (where_a == 0xc0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (is_rsl_bridge || is_nic_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) v = 0x0101; /* subordinate:secondary = 1:1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) else if (is_rad_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) v = 0x0202; /* subordinate:secondary = 2:2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) else if (is_zip_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) v = 0x0303; /* subordinate:secondary = 3:3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) else if (is_dfa_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) v = 0x0404; /* subordinate:secondary = 4:4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (where_a == 0xc4 && is_nic_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Enabled, not-Write, SP=ff, PP=05, BEI=6, ES=4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) v = 0x80ff0564;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (where_a == 0xc8 && is_nic_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) v = 0x00000002; /* Base-L 64-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (where_a == 0xcc && is_nic_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) v = 0xfffffffe; /* MaxOffset-L 64-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (where_a == 0xd0 && is_nic_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) v = 0x00008430; /* NIC Base-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (where_a == 0xd4 && is_nic_bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) v = 0x0000000f; /* MaxOffset-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) set_val(v, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) no_emulation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return pci_generic_config_read(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * All BARs have fixed addresses; ignore BAR writes so they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * don't get corrupted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if ((where >= 0x10 && where < 0x2c) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) (where >= 0x1a4 && where < 0x1bc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* BAR or SR-IOV BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return pci_generic_config_write(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) const struct pci_ecam_ops pci_thunder_ecam_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .bus_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .map_bus = pci_ecam_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .read = thunder_ecam_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .write = thunder_ecam_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #ifdef CONFIG_PCI_HOST_THUNDER_ECAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct of_device_id thunder_ecam_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .compatible = "cavium,pci-host-thunder-ecam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .data = &pci_thunder_ecam_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct platform_driver thunder_ecam_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .of_match_table = thunder_ecam_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .probe = pci_host_common_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) builtin_platform_driver(thunder_ecam_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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