Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  pci-rcar-gen2: internal PCI bus support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2013 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2013 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Valentine Barshak <valentine.barshak@cogentembedded.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include "../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* AHB-PCI Bridge PCI communication registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define RCAR_AHBPCI_PCICOM_OFFSET	0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RCAR_PCIAHB_WIN1_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define RCAR_PCIAHB_WIN2_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RCAR_PCIAHB_PREFETCH0		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RCAR_PCIAHB_PREFETCH4		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RCAR_PCIAHB_PREFETCH8		0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RCAR_PCIAHB_PREFETCH16		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RCAR_AHBPCI_WIN1_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RCAR_AHBPCI_WIN2_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define RCAR_AHBPCI_WIN_CTR_MEM		(3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define RCAR_AHBPCI_WIN_CTR_CFG		(5 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RCAR_AHBPCI_WIN1_HOST		(1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RCAR_AHBPCI_WIN1_DEVICE		(1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RCAR_PCI_INT_ENABLE_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RCAR_PCI_INT_STATUS_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RCAR_PCI_INT_SIGTABORT		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define RCAR_PCI_INT_SIGRETABORT	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define RCAR_PCI_INT_REMABORT		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define RCAR_PCI_INT_PERR		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RCAR_PCI_INT_SIGSERR		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define RCAR_PCI_INT_RESERR		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RCAR_PCI_INT_WIN1ERR		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RCAR_PCI_INT_WIN2ERR		(1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RCAR_PCI_INT_A			(1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RCAR_PCI_INT_B			(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define RCAR_PCI_INT_PME		(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT		| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 				RCAR_PCI_INT_SIGRETABORT	| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 				RCAR_PCI_INT_REMABORT		| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 				RCAR_PCI_INT_PERR		| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 				RCAR_PCI_INT_SIGSERR		| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 				RCAR_PCI_INT_RESERR		| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 				RCAR_PCI_INT_WIN1ERR		| \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 				RCAR_PCI_INT_WIN2ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define RCAR_AHB_BUS_CTR_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define RCAR_AHB_BUS_MMODE_HTRANS	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define RCAR_AHB_BUS_MMODE_BYTE_BURST	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define RCAR_AHB_BUS_MMODE_WR_INCR	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define RCAR_AHB_BUS_MMODE_HBUS_REQ	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define RCAR_AHB_BUS_SMODE_READYCTR	(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define RCAR_AHB_BUS_MODE		(RCAR_AHB_BUS_MMODE_HTRANS |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 					RCAR_AHB_BUS_MMODE_BYTE_BURST |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 					RCAR_AHB_BUS_MMODE_WR_INCR |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					RCAR_AHB_BUS_MMODE_HBUS_REQ |	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 					RCAR_AHB_BUS_SMODE_READYCTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define RCAR_USBCTR_REG			(RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define RCAR_USBCTR_USBH_RST		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define RCAR_USBCTR_PCICLK_MASK		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define RCAR_USBCTR_PLL_RST		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define RCAR_USBCTR_DIRPD		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define RCAR_USBCTR_PCIAHB_WIN2_EN	(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define RCAR_USBCTR_PCIAHB_WIN1_256M	(0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define RCAR_USBCTR_PCIAHB_WIN1_512M	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define RCAR_USBCTR_PCIAHB_WIN1_1G	(2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define RCAR_USBCTR_PCIAHB_WIN1_2G	(3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define RCAR_USBCTR_PCIAHB_WIN1_MASK	(3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define RCAR_PCI_ARBITER_CTR_REG	(RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define RCAR_PCI_ARBITER_PCIREQ0	(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define RCAR_PCI_ARBITER_PCIREQ1	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define RCAR_PCI_ARBITER_PCIBP_MODE	(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define RCAR_PCI_UNIT_REV_REG		(RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) struct rcar_pci_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct resource mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct resource *cfg_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* PCI configuration space operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				       int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct rcar_pci_priv *priv = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	int slot, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	if (!pci_is_root_bus(bus) || PCI_FUNC(devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/* Only one EHCI/OHCI device built-in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	slot = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (slot > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/* bridge logic only has registers to 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (slot == 0x0 && where >= 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		     RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return priv->reg + (slot >> 1) * 0x100 + where;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_PCI_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* if debug enabled, then attach an error handler irq to the bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct rcar_pci_priv *priv = pw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	if (status & RCAR_PCI_INT_ALLERRORS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		dev_err(dev, "error irq: status %08x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		/* clear the error(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		iowrite32(status & RCAR_PCI_INT_ALLERRORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			  priv->reg + RCAR_PCI_INT_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ret = devm_request_irq(dev, priv->irq, rcar_pci_err_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			       IRQF_SHARED, "error irq", priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		dev_err(dev, "cannot claim IRQ for error handling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	val |= RCAR_PCI_INT_ALLERRORS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* PCI host controller setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void rcar_pci_setup(struct rcar_pci_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	void __iomem *reg = priv->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct resource_entry *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned long window_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	unsigned long window_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	unsigned long window_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	entry = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (!entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		window_addr = 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		window_pci = 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		window_size = SZ_1G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		window_addr = entry->res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		window_pci = entry->res->start - entry->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		window_size = resource_size(entry->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	dev_info(dev, "PCI: revision %x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/* Disable Direct Power Down State and assert reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	iowrite32(val, reg + RCAR_USBCTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	udelay(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* De-assert reset and reset PCIAHB window1 size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* Setup PCIAHB window1 size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	switch (window_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	case SZ_2G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	case SZ_1G:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	case SZ_512M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		pr_warn("unknown window size %ld - defaulting to 256M\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			window_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		window_size = SZ_256M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	case SZ_256M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	iowrite32(val, reg + RCAR_USBCTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/* Configure AHB master and slave modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/* Configure PCI arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	       RCAR_PCI_ARBITER_PCIBP_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* PCI-AHB mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	iowrite32(window_addr | RCAR_PCIAHB_PREFETCH16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		  reg + RCAR_PCIAHB_WIN1_CTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* AHB-PCI mapping: OHCI/EHCI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	/* Enable AHB-PCI bridge PCI configuration access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		  reg + RCAR_AHBPCI_WIN1_CTR_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	/* Set PCI-AHB Window1 address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	iowrite32(window_pci | PCI_BASE_ADDRESS_MEM_PREFETCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		  reg + PCI_BASE_ADDRESS_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/* Set AHB-PCI bridge PCI communication area address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	iowrite32(val, reg + PCI_BASE_ADDRESS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	val = ioread32(reg + PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	       PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	iowrite32(val, reg + PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	/* Enable PCI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		  reg + RCAR_PCI_INT_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	rcar_pci_setup_errirq(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct pci_ops rcar_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.map_bus = rcar_pci_cfg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.read	= pci_generic_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.write	= pci_generic_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int rcar_pci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct resource *cfg_res, *mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct rcar_pci_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	priv = pci_host_bridge_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	bridge->sysdata = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	reg = devm_ioremap_resource(dev, cfg_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (!mem_res || !mem_res->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (mem_res->start & 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	priv->mem_res = *mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	priv->cfg_res = cfg_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	priv->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	priv->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (priv->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		dev_err(dev, "no valid irq found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		return priv->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	bridge->ops = &rcar_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	pci_add_flags(PCI_REASSIGN_ALL_BUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	rcar_pci_setup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	return pci_host_probe(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct of_device_id rcar_pci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	{ .compatible = "renesas,pci-r8a7790", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	{ .compatible = "renesas,pci-r8a7791", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	{ .compatible = "renesas,pci-r8a7794", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	{ .compatible = "renesas,pci-rcar-gen2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct platform_driver rcar_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		.name = "pci-rcar-gen2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.of_match_table = rcar_pci_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.probe = rcar_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) builtin_platform_driver(rcar_pci_driver);