^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Loongson PCI Host Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Device IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DEV_PCIE_PORT_0 0x7a09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DEV_PCIE_PORT_1 0x7a19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DEV_PCIE_PORT_2 0x7a29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DEV_LS2K_APB 0x7a02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DEV_LS7A_CONF 0x7a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DEV_LS7A_LPC 0x7a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FLAG_CFG0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FLAG_CFG1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FLAG_DEV_FIX BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct loongson_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *cfg0_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *cfg1_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Fixup wrong class code in PCIe bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void bridge_class_quirk(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) dev->class = PCI_CLASS_BRIDGE_PCI << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEV_PCIE_PORT_0, bridge_class_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DEV_PCIE_PORT_1, bridge_class_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DEV_PCIE_PORT_2, bridge_class_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void system_bus_quirk(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * The address space consumed by these devices is outside the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * resources of the host bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pdev->mmio_always_on = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pdev->non_compliant_bars = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEV_LS2K_APB, system_bus_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEV_LS7A_CONF, system_bus_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEV_LS7A_LPC, system_bus_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void loongson_mrrs_quirk(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct pci_bus *bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const struct pci_device_id bridge_devids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* look for the matching bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) while (!pci_is_root_bus(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) bus = bus->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Some Loongson PCIe ports have a h/w limitation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * 256 bytes maximum read request size. They can't handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * anything larger than this. So force this limit on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * any devices attached under these ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (pci_match_id(bridge_devids, bridge)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (pcie_get_readrq(dev) > 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pci_info(dev, "limiting MRRS to 256\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pcie_set_readrq(dev, 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void __iomem *cfg1_map(struct loongson_pci *priv, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int devfn, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long addroff = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (bus != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) addroff |= BIT(28); /* Type 1 Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) addroff |= (where & 0xff) | ((where & 0xf00) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) addroff |= (bus << 16) | (devfn << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return priv->cfg1_base + addroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void __iomem *cfg0_map(struct loongson_pci *priv, int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int devfn, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long addroff = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (bus != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) addroff |= BIT(24); /* Type 1 Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) addroff |= (bus << 16) | (devfn << 8) | where;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return priv->cfg0_base + addroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned char busnum = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct loongson_pci *priv = pci_host_bridge_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Do not read more than one device on the bus other than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * the host bus. For our hardware the root bus is always bus 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (priv->flags & FLAG_DEV_FIX && busnum != 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PCI_SLOT(devfn) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* CFG0 can only access standard space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (where < PCI_CFG_SPACE_SIZE && priv->cfg0_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return cfg0_map(priv, busnum, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* CFG1 can access extended space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (where < PCI_CFG_SPACE_EXP_SIZE && priv->cfg1_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return cfg1_map(priv, busnum, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) irq = of_irq_parse_and_map_pci(dev, slot, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Care i8259 legacy systems */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* i8259 only have 15 IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (val > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* H/w only accept 32-bit PCI operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct pci_ops loongson_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .map_bus = pci_loongson_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .read = pci_generic_config_read32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .write = pci_generic_config_write32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct of_device_id loongson_pci_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .compatible = "loongson,ls2k-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .compatible = "loongson,ls7a-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { .compatible = "loongson,rs780e-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .data = (void *)(FLAG_CFG0), },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int loongson_pci_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct loongson_pci *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct resource *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) priv = pci_host_bridge_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) priv->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) priv->flags = (unsigned long)of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(dev, "missing mem resources for cfg0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (IS_ERR(priv->cfg0_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return PTR_ERR(priv->cfg0_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* CFG1 is optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (priv->flags & FLAG_CFG1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_info(dev, "missing mem resource for cfg1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (IS_ERR(priv->cfg1_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) priv->cfg1_base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) bridge->sysdata = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) bridge->ops = &loongson_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bridge->map_irq = loongson_map_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return pci_host_probe(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct platform_driver loongson_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .name = "loongson-pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .of_match_table = loongson_pci_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .probe = loongson_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) builtin_platform_driver(loongson_pci_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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