^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Aardvark PCIe controller, used on Marvell Armada
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * 3700.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2016 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "../pci-bridge-emul.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* PCIe core registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCIE_CORE_DEV_ID_REG 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCIE_CORE_CMD_STATUS_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCIE_CORE_DEV_REV_REG 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCIE_CORE_PCIEXP_CAP 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCIE_CORE_ERR_CAPCTL_REG 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCIE_CORE_INT_A_ASSERT_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCIE_CORE_INT_B_ASSERT_ENABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCIE_CORE_INT_C_ASSERT_ENABLE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCIE_CORE_INT_D_ASSERT_ENABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* PIO registers base address and register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PIO_BASE_ADDR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PIO_STAT (PIO_BASE_ADDR + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PIO_COMPLETION_STATUS_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PIO_COMPLETION_STATUS_OK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PIO_COMPLETION_STATUS_UR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PIO_COMPLETION_STATUS_CRS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PIO_COMPLETION_STATUS_CA 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PIO_NON_POSTED_REQ BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PIO_ERR_STATUS BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PIO_START (PIO_BASE_ADDR + 0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PIO_ISR (PIO_BASE_ADDR + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Aardvark Control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CONTROL_BASE_ADDR 0x4800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCIE_GEN_SEL_MSK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCIE_GEN_SEL_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SPEED_GEN_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPEED_GEN_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPEED_GEN_3 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IS_RC_MSK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IS_RC_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LANE_CNT_MSK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LANE_CNT_SHIFT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LINK_TRAINING_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LEGACY_INTA BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LEGACY_INTB BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LEGACY_INTC BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LEGACY_INTD BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HOT_RESET_GEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PCIE_CORE_CTRL2_RESERVED 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCIE_CORE_REF_CLK_RX_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCIE_MSG_PM_PME_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCIE_ISR0_ALL_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCIE_ISR1_FLUSH BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCIE_ISR1_ALL_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCIE_MSI_DATA_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* PCIe window configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define OB_WIN_BASE_ADDR 0x4c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OB_WIN_BLOCK_SIZE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define OB_WIN_COUNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) OB_WIN_BLOCK_SIZE * (win) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OB_WIN_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OB_WIN_FUNC_NUM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OB_WIN_FUNC_NUM_ENABLE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OB_WIN_BUS_NUM_BITS_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OB_WIN_MSG_CODE_ENABLE BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OB_WIN_MSG_CODE_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define OB_WIN_ATTR_ENABLE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OB_WIN_ATTR_TC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define OB_WIN_ATTR_RELAXED BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OB_WIN_ATTR_NOSNOOP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OB_WIN_ATTR_POISON BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OB_WIN_ATTR_IDO BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OB_WIN_TYPE_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OB_WIN_TYPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OB_WIN_TYPE_MEM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OB_WIN_TYPE_IO 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define OB_WIN_TYPE_CONFIG_TYPE0 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OB_WIN_TYPE_CONFIG_TYPE1 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OB_WIN_TYPE_MSG 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* LMI registers base address and register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LMI_BASE_ADDR 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CFG_REG (LMI_BASE_ADDR + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LTSSM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LTSSM_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RC_BAR_CONFIG 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* LTSSM values in CFG_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) LTSSM_DETECT_QUIET = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) LTSSM_DETECT_ACTIVE = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) LTSSM_POLLING_ACTIVE = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) LTSSM_POLLING_COMPLIANCE = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) LTSSM_POLLING_CONFIGURATION = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) LTSSM_CONFIG_LINKWIDTH_START = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) LTSSM_CONFIG_LINKWIDTH_ACCEPT = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) LTSSM_CONFIG_LANENUM_ACCEPT = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) LTSSM_CONFIG_LANENUM_WAIT = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) LTSSM_CONFIG_COMPLETE = 0x9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) LTSSM_CONFIG_IDLE = 0xa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) LTSSM_RECOVERY_RCVR_LOCK = 0xb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) LTSSM_RECOVERY_SPEED = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) LTSSM_RECOVERY_RCVR_CFG = 0xd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) LTSSM_RECOVERY_IDLE = 0xe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) LTSSM_L0 = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) LTSSM_RX_L0S_ENTRY = 0x11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) LTSSM_RX_L0S_IDLE = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) LTSSM_RX_L0S_FTS = 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) LTSSM_TX_L0S_ENTRY = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) LTSSM_TX_L0S_IDLE = 0x15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) LTSSM_TX_L0S_FTS = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) LTSSM_L1_ENTRY = 0x17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) LTSSM_L1_IDLE = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) LTSSM_L2_IDLE = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) LTSSM_L2_TRANSMIT_WAKE = 0x1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) LTSSM_DISABLED = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) LTSSM_LOOPBACK_ENTRY_MASTER = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) LTSSM_LOOPBACK_EXIT_MASTER = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) LTSSM_LOOPBACK_EXIT_SLAVE = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) LTSSM_HOT_RESET = 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 0x29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) LTSSM_RECOVERY_EQUALIZATION_PHASE2 = 0x2a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) LTSSM_RECOVERY_EQUALIZATION_PHASE3 = 0x2b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* PCIe core controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CTRL_CORE_BASE_ADDR 0x18000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CTRL_MODE_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CTRL_MODE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PCIE_CORE_MODE_DIRECT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define PCIE_CORE_MODE_COMMAND 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* PCIe Central Interrupts Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CENTRAL_INT_BASE_ADDR 0x1b000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PCIE_IRQ_CMDQ_INT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PCIE_IRQ_DMA_INT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PCIE_IRQ_IB_DXFERDONE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PCIE_IRQ_OB_DXFERDONE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PCIE_IRQ_OB_RXFERDONE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define PCIE_IRQ_COMPQ_INT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PCIE_IRQ_CORE_INT BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PCIE_IRQ_CORE_INT_PIO BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PCIE_IRQ_DPMU_INT BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PCIE_IRQ_MSI_INT1_DET BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PCIE_IRQ_MSI_INT2_DET BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PCIE_IRQ_RC_DBELL_DET BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PCIE_IRQ_EP_STATUS BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PCIE_IRQ_ALL_MASK GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Transaction types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PCIE_CONFIG_RD_TYPE0 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PCIE_CONFIG_RD_TYPE1 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PCIE_CONFIG_WR_TYPE0 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PCIE_CONFIG_WR_TYPE1 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define PCIE_CONF_ADDR(bus, devfn, where) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PIO_RETRY_CNT 750000 /* 1.5 s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PIO_RETRY_DELAY 2 /* 2 us*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define LINK_WAIT_MAX_RETRIES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define LINK_WAIT_USLEEP_MIN 90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define LINK_WAIT_USLEEP_MAX 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define RETRAIN_WAIT_MAX_RETRIES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define RETRAIN_WAIT_USLEEP_US 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MSI_IRQ_NUM 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CFG_RD_CRS_VAL 0xffff0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct advk_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) phys_addr_t match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) phys_addr_t remap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) phys_addr_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 actions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) } wins[OB_WIN_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 wins_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) raw_spinlock_t irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct irq_domain *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct irq_domain *msi_inner_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct irq_chip msi_bottom_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct irq_chip msi_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct msi_domain_info msi_domain_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct mutex msi_used_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u16 msi_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int link_gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct pci_bridge_emul bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) writel(val, pcie->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return readl(pcie->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 ltssm_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) val = advk_readl(pcie, CFG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ltssm_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static inline bool advk_pcie_link_up(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* check if LTSSM is in normal operation - some L* state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 ltssm_state = advk_pcie_ltssm_state(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static inline bool advk_pcie_link_active(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * According to PCIe Base specification 3.0, Table 4-14: Link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Status Mapped to the LTSSM, and 4.2.6.3.6 Configuration.Idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * is Link Up mapped to LTSSM Configuration.Idle, Recovery, L0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * L0s, L1 and L2 states. And according to 3.2.1. Data Link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Control and Management State Machine Rules is DL Up status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * reported in DL Active state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u8 ltssm_state = advk_pcie_ltssm_state(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ltssm_state >= LTSSM_CONFIG_IDLE && ltssm_state < LTSSM_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static inline bool advk_pcie_link_training(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * According to PCIe Base specification 3.0, Table 4-14: Link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * Status Mapped to the LTSSM is Link Training mapped to LTSSM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Configuration and Recovery states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 ltssm_state = advk_pcie_ltssm_state(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ((ltssm_state >= LTSSM_CONFIG_LINKWIDTH_START &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ltssm_state < LTSSM_L0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) (ltssm_state >= LTSSM_RECOVERY_EQUALIZATION_PHASE0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ltssm_state <= LTSSM_RECOVERY_EQUALIZATION_PHASE3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* check if the link is up or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (advk_pcie_link_up(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) size_t retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (advk_pcie_link_training(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) udelay(RETRAIN_WAIT_USLEEP_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static void advk_pcie_issue_perst(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!pcie->reset_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* 10ms delay is needed for some cards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) gpiod_set_value_cansleep(pcie->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) gpiod_set_value_cansleep(pcie->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void advk_pcie_train_link(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct device *dev = &pcie->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Setup PCIe rev / gen compliance based on device tree property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * 'max-link-speed' which also forces maximal link speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) reg &= ~PCIE_GEN_SEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (pcie->link_gen == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) reg |= SPEED_GEN_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) else if (pcie->link_gen == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) reg |= SPEED_GEN_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) reg |= SPEED_GEN_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * Set maximal link speed value also into PCIe Link Control 2 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Armada 3700 Functional Specification says that default value is based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * on SPEED_GEN but tests showed that default value is always 8.0 GT/s.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) reg &= ~PCI_EXP_LNKCTL2_TLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (pcie->link_gen == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) reg |= PCI_EXP_LNKCTL2_TLS_8_0GT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) else if (pcie->link_gen == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) reg |= PCI_EXP_LNKCTL2_TLS_5_0GT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) reg |= PCI_EXP_LNKCTL2_TLS_2_5GT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Enable link training after selecting PCIe generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) reg |= LINK_TRAINING_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Reset PCIe card via PERST# signal. Some cards are not detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * during link training when they are in some non-initial state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) advk_pcie_issue_perst(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * PERST# signal could have been asserted by pinctrl subsystem before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * probe() callback has been called or issued explicitly by reset gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * function advk_pcie_issue_perst(), making the endpoint going into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * fundamental reset. As required by PCI Express spec (PCI Express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * Base Specification, REV. 4.0 PCI Express, February 19 2014, 6.6.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Conventional Reset) a delay for at least 100ms after such a reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * before sending a Configuration Request to the device is needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * So wait until PCIe link is up. Function advk_pcie_wait_for_link()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * waits for link at least 900ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = advk_pcie_wait_for_link(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(dev, "link never came up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_info(dev, "link up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Set PCIe address window register which could be used for memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) phys_addr_t match, phys_addr_t remap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) phys_addr_t mask, u32 actions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) advk_writel(pcie, OB_WIN_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static void advk_pcie_setup_hw(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Configure PCIe Reference clock. Direction is from the PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * controller to the endpoint card, so enable transmitting of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * Reference clock differential signal off-chip and disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * receiving off-chip differential signal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) reg |= PCIE_CORE_REF_CLK_TX_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) reg &= ~PCIE_CORE_REF_CLK_RX_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Set to Direct mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) reg = advk_readl(pcie, CTRL_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) advk_writel(pcie, reg, CTRL_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Set PCI global control register to RC mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) reg |= (IS_RC_MSK << IS_RC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * id in high 16 bits. Updating this register changes readback value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * for erratum 4.1: "The value of device and vendor ID is incorrect".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) advk_writel(pcie, reg, VENDOR_ID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * Change Class Code of PCI Bridge device to PCI Bridge (0x600400),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * because the default value is Mass storage controller (0x010400).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Note that this Aardvark PCI Bridge does not have compliant Type 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * Configuration Space and it even cannot be accessed via Aardvark's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * PCI config space access method. Something like config space is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * available in internal Aardvark registers starting at offset 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * and is reported as Type 0. In range 0x10 - 0x34 it has totally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * different registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * Therefore driver uses emulation of PCI Bridge which emulates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * access to configuration space via internal Aardvark registers or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * emulated configuration buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) reg &= ~0xffffff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Disable Root Bridge I/O space, memory space and bus mastering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Set Advanced Error Capabilities and Control PF0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Set PCIe Device Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) reg &= ~PCI_EXP_DEVCTL_READRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) reg |= PCI_EXP_DEVCTL_PAYLOAD_512B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) reg |= PCI_EXP_DEVCTL_READRQ_512B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Program PCIe Control 2 to disable strict ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) reg = PCIE_CORE_CTRL2_RESERVED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PCIE_CORE_CTRL2_TD_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Set lane X1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) reg &= ~LANE_CNT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) reg |= LANE_COUNT_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Enable MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Disable All ISR0/1 Sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) reg = PCIE_ISR0_ALL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) reg &= ~PCIE_ISR0_MSI_INT_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Unmask all MSIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Enable summary interrupt for GIC SPI source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * Enable AXI address window location generation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * When it is enabled, the default outbound window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * configurations (Default User Field: 0xD0074CFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * are used to transparent address translation for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * the outbound transactions. Thus, PCIe address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * windows are not required for transparent memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * access when default outbound window configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * is set for memory access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Set memory access in Default User Field so it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * is not required to configure PCIe address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * transparent memory access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * Bypass the address window mapping for PIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Since PIO access already contains all required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * info over AXI interface by PIO registers, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * address window is not required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) reg = advk_readl(pcie, PIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) reg |= PIO_CTRL_ADDR_WIN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) advk_writel(pcie, reg, PIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * Configure PCIe address windows for non-memory or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * non-transparent access as by default PCIe uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * transparent memory access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) for (i = 0; i < pcie->wins_count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) advk_pcie_set_ob_win(pcie, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pcie->wins[i].match, pcie->wins[i].remap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pcie->wins[i].mask, pcie->wins[i].actions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Disable remaining PCIe outbound windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) for (i = pcie->wins_count; i < OB_WIN_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) advk_pcie_disable_ob_win(pcie, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) advk_pcie_train_link(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct device *dev = &pcie->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) char *strcomp_status, *str_posted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) reg = advk_readl(pcie, PIO_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) status = (reg & PIO_COMPLETION_STATUS_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PIO_COMPLETION_STATUS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * According to HW spec, the PIO status check sequence as below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * 1) even if COMPLETION_STATUS(bit9:7) indicates successful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * it still needs to check Error Status(bit11), only when this bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * indicates no error happen, the operation is successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * 2) value Unsupported Request(1) of COMPLETION_STATUS(bit9:7) only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * means a PIO write error, and for PIO read it is successful with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * a read value of 0xFFFFFFFF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * 3) value Completion Retry Status(CRS) of COMPLETION_STATUS(bit9:7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * only means a PIO write error, and for PIO read it is successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * with a read value of 0xFFFF0001.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * 4) value Completer Abort (CA) of COMPLETION_STATUS(bit9:7) means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * error for both PIO read and PIO write operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * 5) other errors are indicated as 'unknown'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) switch (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) case PIO_COMPLETION_STATUS_OK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (reg & PIO_ERR_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) strcomp_status = "COMP_ERR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Get the read result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) *val = advk_readl(pcie, PIO_RD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* No error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) strcomp_status = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case PIO_COMPLETION_STATUS_UR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) strcomp_status = "UR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) case PIO_COMPLETION_STATUS_CRS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (allow_crs && val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* PCIe r4.0, sec 2.3.2, says:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * If CRS Software Visibility is enabled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * For a Configuration Read Request that includes both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * bytes of the Vendor ID field of a device Function's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * Configuration Space Header, the Root Complex must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * complete the Request to the host by returning a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * read-data value of 0001h for the Vendor ID field and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * all '1's for any additional bytes included in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * So CRS in this case is not an error status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) *val = CFG_RD_CRS_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) strcomp_status = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* PCIe r4.0, sec 2.3.2, says:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * If CRS Software Visibility is not enabled, the Root Complex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * must re-issue the Configuration Request as a new Request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * If CRS Software Visibility is enabled: For a Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * Write Request or for any other Configuration Read Request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * the Root Complex must re-issue the Configuration Request as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * a new Request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * A Root Complex implementation may choose to limit the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * of Configuration Request/CRS Completion Status loops before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * determining that something is wrong with the target of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * Request and taking appropriate action, e.g., complete the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * Request to the host as a failed transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * So return -EAGAIN and caller (pci-aardvark.c driver) will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * re-issue request again up to the PIO_RETRY_CNT retries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) strcomp_status = "CRS";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case PIO_COMPLETION_STATUS_CA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) strcomp_status = "CA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = -ECANCELED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) strcomp_status = "Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (!strcomp_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (reg & PIO_NON_POSTED_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) str_posted = "Non-posted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) str_posted = "Posted";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dev_dbg(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int advk_pcie_wait_pio(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct device *dev = &pcie->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) for (i = 1; i <= PIO_RETRY_CNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u32 start, isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) start = advk_readl(pcie, PIO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) isr = advk_readl(pcie, PIO_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (!start && isr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) udelay(PIO_RETRY_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_err(dev, "PIO read/write transfer time out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static pci_bridge_emul_read_status_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) advk_pci_bridge_emul_base_conf_read(struct pci_bridge_emul *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int reg, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct advk_pcie *pcie = bridge->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case PCI_COMMAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return PCI_BRIDGE_EMUL_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case PCI_INTERRUPT_LINE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * From the whole 32bit register we support reading from HW only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * one bit: PCI_BRIDGE_CTL_BUS_RESET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * Other bits are retrieved only from emulated config buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) __le32 *cfgspace = (__le32 *)&bridge->conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) val |= PCI_BRIDGE_CTL_BUS_RESET << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) *value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return PCI_BRIDGE_EMUL_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return PCI_BRIDGE_EMUL_NOT_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) advk_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int reg, u32 old, u32 new, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct advk_pcie *pcie = bridge->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) case PCI_COMMAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) case PCI_INTERRUPT_LINE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (new & (PCI_BRIDGE_CTL_BUS_RESET << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) val |= HOT_RESET_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) val &= ~HOT_RESET_GEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) advk_writel(pcie, val, PCIE_CORE_CTRL1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static pci_bridge_emul_read_status_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int reg, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct advk_pcie *pcie = bridge->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case PCI_EXP_SLTCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) *value = PCI_EXP_SLTSTA_PDS << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return PCI_BRIDGE_EMUL_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) case PCI_EXP_RTCTL: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) *value |= le16_to_cpu(bridge->pcie_conf.rootctl) & PCI_EXP_RTCTL_CRSSVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) *value |= PCI_EXP_RTCAP_CRSVIS << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return PCI_BRIDGE_EMUL_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) case PCI_EXP_RTSTA: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) *value = msglog >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (isr0 & PCIE_MSG_PM_PME_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) *value |= PCI_EXP_RTSTA_PME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return PCI_BRIDGE_EMUL_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case PCI_EXP_LNKCAP: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * But support for PCI_EXP_LNKSTA_DLLLA is emulated via ltssm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * state so explicitly enable PCI_EXP_LNKCAP_DLLLARC flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) val |= PCI_EXP_LNKCAP_DLLLARC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) *value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return PCI_BRIDGE_EMUL_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case PCI_EXP_LNKCTL: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ~(PCI_EXP_LNKSTA_LT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (advk_pcie_link_training(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) val |= (PCI_EXP_LNKSTA_LT << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (advk_pcie_link_active(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) val |= (PCI_EXP_LNKSTA_DLLLA << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) *value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return PCI_BRIDGE_EMUL_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case PCI_EXP_DEVCAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) case PCI_EXP_DEVCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return PCI_BRIDGE_EMUL_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return PCI_BRIDGE_EMUL_NOT_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int reg, u32 old, u32 new, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct advk_pcie *pcie = bridge->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case PCI_EXP_DEVCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case PCI_EXP_LNKCTL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (new & PCI_EXP_LNKCTL_RL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) advk_pcie_wait_for_retrain(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) case PCI_EXP_RTCTL: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* Only mask/unmask PME interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ~PCIE_MSG_PM_PME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if ((new & PCI_EXP_RTCTL_PMEIE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) val |= PCIE_MSG_PM_PME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) case PCI_EXP_RTSTA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) new = (new & PCI_EXP_RTSTA_PME) >> 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) advk_writel(pcie, new, PCIE_ISR0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .read_base = advk_pci_bridge_emul_base_conf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .write_base = advk_pci_bridge_emul_base_conf_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .read_pcie = advk_pci_bridge_emul_pcie_conf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .write_pcie = advk_pci_bridge_emul_pcie_conf_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * Initialize the configuration space of the PCI-to-PCI bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * associated with the given PCIe interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static int advk_sw_pci_bridge_init(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct pci_bridge_emul *bridge = &pcie->bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) bridge->conf.vendor =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) bridge->conf.device =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) bridge->conf.class_revision =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* Support 32 bits I/O addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* Support 64 bits memory pref */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* Support interrupt A for MSI feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* Aardvark HW provides PCIe Capability structure in version 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) bridge->pcie_conf.cap = cpu_to_le16(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* Indicates supports for Completion Retry Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) bridge->has_pcie = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) bridge->data = pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) bridge->ops = &advk_pci_bridge_emul_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return pci_bridge_emul_init(bridge, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * If the link goes down after we check for link-up, nothing bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * happens but the config access times out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static bool advk_pcie_pio_is_running(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct device *dev = &pcie->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * Trying to start a new PIO transfer when previous has not completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * cause External Abort on CPU which results in kernel panic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * SError Interrupt on CPU0, code 0xbf000002 -- SError
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * Kernel panic - not syncing: Asynchronous SError Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * by raw_spin_lock_irqsave() at pci_lock_config() level to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * concurrent calls at the same time. But because PIO transfer may take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * about 1.5s when link is down or card is disconnected, it means that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * advk_pcie_wait_pio() does not always have to wait for completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * Some versions of ARM Trusted Firmware handles this External Abort at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (advk_readl(pcie, PIO_START)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dev_err(dev, "Previous PIO read/write transfer is still running\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct advk_pcie *pcie = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) bool allow_crs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (!advk_pcie_valid_device(pcie, bus, devfn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) *val = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (pci_is_root_bus(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return pci_bridge_emul_conf_read(&pcie->bridge, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * Completion Retry Status is possible to return only when reading all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * 4 bytes from PCI_VENDOR_ID and PCI_DEVICE_ID registers at once and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * CRSSVE flag on Root Bridge is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) allow_crs = (where == PCI_VENDOR_ID) && (size == 4) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PCI_EXP_RTCTL_CRSSVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (advk_pcie_pio_is_running(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) goto try_crs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* Program the control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) reg = advk_readl(pcie, PIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) reg &= ~PIO_CTRL_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (pci_is_root_bus(bus->parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) reg |= PCIE_CONFIG_RD_TYPE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) reg |= PCIE_CONFIG_RD_TYPE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) advk_writel(pcie, reg, PIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Program the address registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) reg = PCIE_CONF_ADDR(bus->number, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) advk_writel(pcie, reg, PIO_ADDR_LS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) advk_writel(pcie, 0, PIO_ADDR_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* Program the data strobe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) retry_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* Clear PIO DONE ISR and start the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) advk_writel(pcie, 1, PIO_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) advk_writel(pcie, 1, PIO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret = advk_pcie_wait_pio(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) goto try_crs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) retry_count += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* Check PIO status and get the read result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) *val = (*val >> (8 * (where & 3))) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) *val = (*val >> (8 * (where & 3))) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) try_crs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * If it is possible, return Completion Retry Status so that caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * tries to issue the request again instead of failing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (allow_crs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) *val = CFG_RD_CRS_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) *val = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return PCIBIOS_SET_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct advk_pcie *pcie = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) u32 data_strobe = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) int retry_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (!advk_pcie_valid_device(pcie, bus, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (pci_is_root_bus(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return pci_bridge_emul_conf_write(&pcie->bridge, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (where % size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return PCIBIOS_SET_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (advk_pcie_pio_is_running(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return PCIBIOS_SET_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Program the control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) reg = advk_readl(pcie, PIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) reg &= ~PIO_CTRL_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (pci_is_root_bus(bus->parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) reg |= PCIE_CONFIG_WR_TYPE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) reg |= PCIE_CONFIG_WR_TYPE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) advk_writel(pcie, reg, PIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) /* Program the address registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) reg = PCIE_CONF_ADDR(bus->number, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) advk_writel(pcie, reg, PIO_ADDR_LS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) advk_writel(pcie, 0, PIO_ADDR_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /* Calculate the write strobe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) offset = where & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) reg = val << (8 * offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) data_strobe = GENMASK(size - 1, 0) << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* Program the data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) advk_writel(pcie, reg, PIO_WR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* Program the data strobe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) retry_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* Clear PIO DONE ISR and start the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) advk_writel(pcie, 1, PIO_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) advk_writel(pcie, 1, PIO_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ret = advk_pcie_wait_pio(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return PCIBIOS_SET_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) retry_count += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ret = advk_pcie_check_pio_status(pcie, false, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static struct pci_ops advk_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .read = advk_pcie_rd_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .write = advk_pcie_wr_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) msg->address_lo = lower_32_bits(msi_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) msg->address_hi = upper_32_bits(msi_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) msg->data = data->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static int advk_msi_set_affinity(struct irq_data *irq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) const struct cpumask *mask, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) unsigned int nr_irqs, void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct advk_pcie *pcie = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) int hwirq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) mutex_lock(&pcie->msi_used_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) 0, nr_irqs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (hwirq >= MSI_IRQ_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) mutex_unlock(&pcie->msi_used_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) bitmap_set(pcie->msi_used, hwirq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) mutex_unlock(&pcie->msi_used_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) for (i = 0; i < nr_irqs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) irq_domain_set_info(domain, virq + i, hwirq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) &pcie->msi_bottom_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) domain->host_data, handle_simple_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static void advk_msi_irq_domain_free(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) unsigned int virq, unsigned int nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct irq_data *d = irq_domain_get_irq_data(domain, virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct advk_pcie *pcie = domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) mutex_lock(&pcie->msi_used_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) mutex_unlock(&pcie->msi_used_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static const struct irq_domain_ops advk_msi_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .alloc = advk_msi_irq_domain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .free = advk_msi_irq_domain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static void advk_pcie_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct advk_pcie *pcie = d->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) raw_spin_lock_irqsave(&pcie->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static void advk_pcie_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct advk_pcie *pcie = d->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) irq_hw_number_t hwirq = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) raw_spin_lock_irqsave(&pcie->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static int advk_pcie_irq_map(struct irq_domain *h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) unsigned int virq, irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct advk_pcie *pcie = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) advk_pcie_irq_mask(irq_get_irq_data(virq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) irq_set_status_flags(virq, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) irq_set_chip_and_handler(virq, &pcie->irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) irq_set_chip_data(virq, pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .map = advk_pcie_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .xlate = irq_domain_xlate_onecell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct device *dev = &pcie->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) struct irq_chip *bottom_ic, *msi_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct msi_domain_info *msi_di;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) phys_addr_t msi_msg_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) mutex_init(&pcie->msi_used_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) bottom_ic = &pcie->msi_bottom_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) bottom_ic->name = "MSI";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) bottom_ic->irq_set_affinity = advk_msi_set_affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) msi_ic = &pcie->msi_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) msi_ic->name = "advk-MSI";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) msi_di = &pcie->msi_domain_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) MSI_FLAG_MULTI_PCI_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) msi_di->chip = msi_ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) msi_msg_phys = virt_to_phys(&pcie->msi_msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) advk_writel(pcie, lower_32_bits(msi_msg_phys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) PCIE_MSI_ADDR_LOW_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) advk_writel(pcie, upper_32_bits(msi_msg_phys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) PCIE_MSI_ADDR_HIGH_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) pcie->msi_inner_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) irq_domain_add_linear(NULL, MSI_IRQ_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) &advk_msi_domain_ops, pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (!pcie->msi_inner_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) pcie->msi_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) pci_msi_create_irq_domain(of_node_to_fwnode(node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) msi_di, pcie->msi_inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (!pcie->msi_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) irq_domain_remove(pcie->msi_inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) irq_domain_remove(pcie->msi_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) irq_domain_remove(pcie->msi_inner_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct device *dev = &pcie->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) struct device_node *pcie_intc_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct irq_chip *irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) raw_spin_lock_init(&pcie->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) pcie_intc_node = of_get_next_child(node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (!pcie_intc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) dev_err(dev, "No PCIe Intc node found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) irq_chip = &pcie->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (!irq_chip->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) goto out_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) irq_chip->irq_mask = advk_pcie_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) irq_chip->irq_mask_ack = advk_pcie_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) irq_chip->irq_unmask = advk_pcie_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) pcie->irq_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) &advk_pcie_irq_domain_ops, pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (!pcie->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) dev_err(dev, "Failed to get a INTx IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) goto out_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) out_put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) of_node_put(pcie_intc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) irq_domain_remove(pcie->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static void advk_pcie_handle_msi(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) u32 msi_val, msi_mask, msi_status, msi_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) u16 msi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) msi_status = msi_val & ~msi_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (!(BIT(msi_idx) & msi_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * msi_idx contains bits [4:0] of the msi_data and msi_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * contains 16bit MSI interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & PCIE_MSI_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) generic_handle_irq(msi_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) PCIE_ISR0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static void advk_pcie_handle_int(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) u32 isr0_val, isr0_mask, isr0_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) u32 isr1_val, isr1_mask, isr1_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) int i, virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* Process MSI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) advk_pcie_handle_msi(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /* Process legacy interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) for (i = 0; i < PCI_NUM_INTX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PCIE_ISR1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) virq = irq_find_mapping(pcie->irq_domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) struct advk_pcie *pcie = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (!(status & PCIE_IRQ_CORE_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) advk_pcie_handle_int(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /* Clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) phy_power_off(pcie->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) phy_exit(pcie->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static int advk_pcie_enable_phy(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (!pcie->phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ret = phy_init(pcie->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) phy_exit(pcie->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ret = phy_power_on(pcie->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (ret == -EOPNOTSUPP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) } else if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) phy_exit(pcie->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static int advk_pcie_setup_phy(struct advk_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) struct device *dev = &pcie->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) pcie->phy = devm_of_phy_get(dev, node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return PTR_ERR(pcie->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* Old bindings miss the PHY handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (IS_ERR(pcie->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) pcie->phy = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) ret = advk_pcie_enable_phy(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) dev_err(dev, "Failed to initialize PHY (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static int advk_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct advk_pcie *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct resource_entry *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) pcie = pci_host_bridge_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) pcie->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) platform_set_drvdata(pdev, pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) resource_list_for_each_entry(entry, &bridge->windows) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) resource_size_t start = entry->res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) resource_size_t size = resource_size(entry->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) unsigned long type = resource_type(entry->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) u64 win_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * Aardvark hardware allows to configure also PCIe window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * for config type 0 and type 1 mapping, but driver uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * only PIO for issuing configuration transfers which does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * not use PCIe window configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (type != IORESOURCE_MEM && type != IORESOURCE_MEM_64 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) type != IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) * Skip transparent memory resources. Default outbound access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) * configuration is set to transparent memory access so it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) * does not need window configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if ((type == IORESOURCE_MEM || type == IORESOURCE_MEM_64) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) entry->offset == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) * The n-th PCIe window is configured by tuple (match, remap, mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * and an access to address A uses this window if A matches the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * match with given mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) * So every PCIe window size must be a power of two and every start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) * address must be aligned to window size. Minimal size is 64 KiB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * because lower 16 bits of mask must be zero. Remapped address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) * may have set only bits from the mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) while (pcie->wins_count < OB_WIN_COUNT && size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* Calculate the largest aligned window size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) win_size = (1ULL << (fls64(size)-1)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) (start ? (1ULL << __ffs64(start)) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) win_size = 1ULL << __ffs64(win_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (win_size < 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) pcie->wins_count, (unsigned long long)start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) (unsigned long long)start + win_size, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) if (type == IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) pcie->wins[pcie->wins_count].match = pci_pio_to_address(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) pcie->wins[pcie->wins_count].match = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) pcie->wins[pcie->wins_count].remap = start - entry->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) pcie->wins[pcie->wins_count].mask = ~(win_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (pcie->wins[pcie->wins_count].remap & (win_size - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) start += win_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) size -= win_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) pcie->wins_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) dev_err(&pcie->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) "Invalid PCIe region [0x%llx-0x%llx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) (unsigned long long)entry->res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) (unsigned long long)entry->res->end + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) pcie->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (IS_ERR(pcie->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) return PTR_ERR(pcie->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) dev_err(dev, "Failed to register interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) "reset-gpios", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) GPIOD_OUT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) "pcie1-reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (ret == -ENOENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) pcie->reset_gpio = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) dev_err(dev, "Failed to get reset-gpio: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) ret = of_pci_get_max_link_speed(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (ret <= 0 || ret > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) pcie->link_gen = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) pcie->link_gen = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ret = advk_pcie_setup_phy(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) advk_pcie_setup_hw(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) ret = advk_sw_pci_bridge_init(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) dev_err(dev, "Failed to register emulated root PCI bridge\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ret = advk_pcie_init_irq_domain(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) dev_err(dev, "Failed to initialize irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ret = advk_pcie_init_msi_irq_domain(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) dev_err(dev, "Failed to initialize irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) advk_pcie_remove_irq_domain(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) bridge->sysdata = pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) bridge->ops = &advk_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ret = pci_host_probe(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) advk_pcie_remove_msi_irq_domain(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) advk_pcie_remove_irq_domain(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) static int advk_pcie_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) struct advk_pcie *pcie = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) pci_lock_rescan_remove();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) pci_stop_root_bus(bridge->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) pci_remove_root_bus(bridge->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) pci_unlock_rescan_remove();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) advk_pcie_remove_msi_irq_domain(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) advk_pcie_remove_irq_domain(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) /* Disable outbound address windows mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) for (i = 0; i < OB_WIN_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) advk_pcie_disable_ob_win(pcie, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static const struct of_device_id advk_pcie_of_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) { .compatible = "marvell,armada-3700-pcie", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) MODULE_DEVICE_TABLE(of, advk_pcie_of_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static struct platform_driver advk_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .name = "advk-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .of_match_table = advk_pcie_of_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .probe = advk_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .remove = advk_pcie_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) module_platform_driver(advk_pcie_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) MODULE_DESCRIPTION("Aardvark PCIe controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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