Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PCIe host controller driver for Mobiveil PCIe Host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2018 Mobiveil Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *	   Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #ifndef _PCIE_MOBIVEIL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define _PCIE_MOBIVEIL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "../../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* register offsets and bit positions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * translation tables are grouped into windows, each window registers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * grouped into blocks of 4 or 16 registers each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PAB_REG_BLOCK_SIZE		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PAB_EXT_REG_BLOCK_SIZE		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PAB_REG_ADDR(offset, win)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	(offset + (win * PAB_REG_BLOCK_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PAB_EXT_REG_ADDR(offset, win)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	(offset + (win * PAB_EXT_REG_BLOCK_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LTSSM_STATUS			0x0404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define  LTSSM_STATUS_L0_MASK		0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define  LTSSM_STATUS_L0		0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PAB_CTRL			0x0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define  AMBA_PIO_ENABLE_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define  PEX_PIO_ENABLE_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define  PAGE_SEL_SHIFT			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define  PAGE_SEL_MASK			0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define  PAGE_LO_MASK			0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define  PAGE_SEL_OFFSET_SHIFT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PAB_ACTIVITY_STAT		0x81c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PAB_AXI_PIO_CTRL		0x0840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define  APIO_EN_MASK			0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PAB_PEX_PIO_CTRL		0x08c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define  PIO_ENABLE_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PAB_INTP_AMBA_MISC_ENB		0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PAB_INTP_AMBA_MISC_STAT		0x0b1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define  PAB_INTP_RESET			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define  PAB_INTP_MSI			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define  PAB_INTP_INTA			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define  PAB_INTP_INTB			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define  PAB_INTP_INTC			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define  PAB_INTP_INTD			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define  PAB_INTP_PCIE_UE		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define  PAB_INTP_IE_PMREDI		BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define  PAB_INTP_IE_EC			BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define  PAB_INTP_MSI_MASK		PAB_INTP_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define  PAB_INTP_INTX_MASK		(PAB_INTP_INTA | PAB_INTP_INTB |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 					PAB_INTP_INTC | PAB_INTP_INTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PAB_AXI_AMAP_CTRL(win)		PAB_REG_ADDR(0x0ba0, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define  WIN_ENABLE_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define  WIN_TYPE_SHIFT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define  WIN_TYPE_MASK			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define  WIN_SIZE_MASK			0xfffffc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PAB_EXT_AXI_AMAP_SIZE(win)	PAB_EXT_REG_ADDR(0xbaf0, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PAB_EXT_AXI_AMAP_AXI_WIN(win)	PAB_EXT_REG_ADDR(0x80a0, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PAB_AXI_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x0ba4, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define  AXI_WINDOW_ALIGN_MASK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PAB_AXI_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x0ba8, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define  PAB_BUS_SHIFT			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define  PAB_DEVICE_SHIFT		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define  PAB_FUNCTION_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define PAB_AXI_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x0bac, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define PAB_INTP_AXI_PIO_CLASS		0x474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define PAB_PEX_AMAP_CTRL(win)		PAB_REG_ADDR(0x4ba0, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define  AMAP_CTRL_EN_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define  AMAP_CTRL_TYPE_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define  AMAP_CTRL_TYPE_MASK		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define PAB_EXT_PEX_AMAP_SIZEN(win)	PAB_EXT_REG_ADDR(0xbef0, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define PAB_EXT_PEX_AMAP_AXI_WIN(win)	PAB_EXT_REG_ADDR(0xb4a0, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define PAB_PEX_AMAP_AXI_WIN(win)	PAB_REG_ADDR(0x4ba4, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define PAB_PEX_AMAP_PEX_WIN_L(win)	PAB_REG_ADDR(0x4ba8, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define PAB_PEX_AMAP_PEX_WIN_H(win)	PAB_REG_ADDR(0x4bac, win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* starting offset of INTX bits in status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PAB_INTX_START			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* supported number of MSI interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCI_NUM_MSI			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* MSI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MSI_BASE_LO_OFFSET		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MSI_BASE_HI_OFFSET		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MSI_SIZE_OFFSET			0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MSI_ENABLE_OFFSET		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MSI_STATUS_OFFSET		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MSI_DATA_OFFSET			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MSI_ADDR_L_OFFSET		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MSI_ADDR_H_OFFSET		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* outbound and inbound window definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WIN_NUM_0			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WIN_NUM_1			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CFG_WINDOW_TYPE			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IO_WINDOW_TYPE			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MEM_WINDOW_TYPE			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IB_WIN_SIZE			((u64)256 * 1024 * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MAX_PIO_WINDOWS			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Parameters for the waiting for link up routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LINK_WAIT_MAX_RETRIES		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LINK_WAIT_MIN			90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LINK_WAIT_MAX			100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PAGED_ADDR_BNDRY		0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OFFSET_TO_PAGE_ADDR(off)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OFFSET_TO_PAGE_IDX(off)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct mobiveil_msi {			/* MSI information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct mutex lock;		/* protect bitmap variable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct irq_domain *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct irq_domain *dev_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	phys_addr_t msi_pages_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	int num_of_vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mobiveil_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct mobiveil_rp_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int (*interrupt_init)(struct mobiveil_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct mobiveil_root_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	void __iomem *config_axi_slave_base;	/* endpoint config base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct resource *ob_io_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct mobiveil_rp_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	raw_spinlock_t intx_mask_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct irq_domain *intx_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct mobiveil_msi msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mobiveil_pab_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int (*link_up)(struct mobiveil_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct mobiveil_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	void __iomem *csr_axi_slave_base;	/* root port config base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	void __iomem *apb_csr_base;	/* MSI register base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	phys_addr_t pcie_reg_base;	/* Physical PCIe Controller Base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int apio_wins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	int ppio_wins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int ob_wins_configured;		/* configured outbound windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int ib_wins_configured;		/* configured inbound windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	const struct mobiveil_pab_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct mobiveil_root_port rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			u64 pci_addr, u32 type, u64 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			u64 pci_addr, u32 type, u64 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline u32 mobiveil_csr_readl(struct mobiveil_pcie *pcie, u32 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return mobiveil_csr_read(pcie, off, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static inline u16 mobiveil_csr_readw(struct mobiveil_pcie *pcie, u32 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return mobiveil_csr_read(pcie, off, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static inline u8 mobiveil_csr_readb(struct mobiveil_pcie *pcie, u32 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return mobiveil_csr_read(pcie, off, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline void mobiveil_csr_writel(struct mobiveil_pcie *pcie, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				       u32 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	mobiveil_csr_write(pcie, val, off, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static inline void mobiveil_csr_writew(struct mobiveil_pcie *pcie, u16 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				       u32 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	mobiveil_csr_write(pcie, val, off, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static inline void mobiveil_csr_writeb(struct mobiveil_pcie *pcie, u8 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				       u32 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	mobiveil_csr_write(pcie, val, off, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif /* _PCIE_MOBIVEIL_H */