^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe host controller driver for Mobiveil PCIe Host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018 Mobiveil Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "pcie-mobiveil.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * mobiveil_pcie_sel_page - routine to access paged register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * for this scheme to work extracted higher 6 bits of the offset will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * written to pg_sel field of PAB_CTRL register and rest of the lower 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (off < PAGED_ADDR_BNDRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* For directly accessed registers, clear the pg_sel field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mobiveil_pcie_sel_page(pcie, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return pcie->csr_axi_slave_base + off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if ((uintptr_t)addr & (size - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *val = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *val = readw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *val = readb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if ((uintptr_t)addr & (size - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) writel(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) writew(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writeb(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) addr = mobiveil_pcie_comp_addr(pcie, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = mobiveil_pcie_read(addr, size, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(&pcie->pdev->dev, "read CSR address failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void mobiveil_csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) addr = mobiveil_pcie_comp_addr(pcie, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = mobiveil_pcie_write(addr, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dev_err(&pcie->pdev->dev, "write CSR address failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (pcie->ops->link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return pcie->ops->link_up(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return (mobiveil_csr_readl(pcie, LTSSM_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void program_ib_windows(struct mobiveil_pcie *pcie, int win_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u64 size64 = ~(size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (win_num >= pcie->ppio_wins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_err(&pcie->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "ERROR: max inbound windows reached !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) value = mobiveil_csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT | WIN_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) value |= type << AMAP_CTRL_TYPE_SHIFT | 1 << AMAP_CTRL_EN_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (lower_32_bits(size64) & WIN_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mobiveil_csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mobiveil_csr_writel(pcie, upper_32_bits(size64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PAB_EXT_PEX_AMAP_SIZEN(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mobiveil_csr_writel(pcie, lower_32_bits(cpu_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PAB_PEX_AMAP_AXI_WIN(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PAB_PEX_AMAP_PEX_WIN_L(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PAB_PEX_AMAP_PEX_WIN_H(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pcie->ib_wins_configured++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * routine to program the outbound windows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void program_ob_windows(struct mobiveil_pcie *pcie, int win_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u64 size64 = ~(size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (win_num >= pcie->apio_wins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(&pcie->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "ERROR: max outbound windows reached !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * to 4 KB in PAB_AXI_AMAP_CTRL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) value = mobiveil_csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT | WIN_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) (lower_32_bits(size64) & WIN_SIZE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mobiveil_csr_writel(pcie, upper_32_bits(size64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PAB_EXT_AXI_AMAP_SIZE(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * program AXI window base with appropriate value in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * PAB_AXI_AMAP_AXI_WIN0 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mobiveil_csr_writel(pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PAB_AXI_AMAP_AXI_WIN(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mobiveil_csr_writel(pcie, upper_32_bits(cpu_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mobiveil_csr_writel(pcie, lower_32_bits(pci_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PAB_AXI_AMAP_PEX_WIN_L(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mobiveil_csr_writel(pcie, upper_32_bits(pci_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PAB_AXI_AMAP_PEX_WIN_H(win_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pcie->ob_wins_configured++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* check if the link is up or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (mobiveil_pcie_link_up(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_err(&pcie->pdev->dev, "link never came up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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