Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PCIe host controller driver for UniPhier SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2018 Socionext Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PCL_PINCTRL0			0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PCL_PERST_PLDN_REGEN		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PCL_PERST_NOE_REGEN		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PCL_PERST_OUT_REGEN		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PCL_PERST_PLDN_REGVAL		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PCL_PERST_NOE_REGVAL		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PCL_PERST_OUT_REGVAL		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PCL_PIPEMON			0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PCL_PCLK_ALIVE			BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PCL_MODE			0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PCL_MODE_REGEN			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PCL_MODE_REGVAL			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PCL_APP_READY_CTRL		0x8008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PCL_APP_LTSSM_ENABLE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PCL_APP_PM0			0x8078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PCL_SYS_AUX_PWR_DET		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PCL_RCV_INT			0x8108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PCL_RCV_INT_ALL_ENABLE		GENMASK(20, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PCL_CFG_BW_MGT_STATUS		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PCL_CFG_LINK_AUTO_BW_STATUS	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PCL_CFG_AER_RC_ERR_MSI_STATUS	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PCL_CFG_PME_MSI_STATUS		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PCL_RCV_INTX			0x810c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PCL_RCV_INTX_ALL_ENABLE		GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PCL_RCV_INTX_ALL_MASK		GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PCL_RCV_INTX_MASK_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PCL_RCV_INTX_ALL_STATUS		GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PCL_RCV_INTX_STATUS_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PCL_STATUS_LINK			0x8140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PCL_RDLH_LINK_UP		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PCL_XMLH_LINK_UP		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct uniphier_pcie_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct dw_pcie pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct irq_domain *legacy_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define to_uniphier_pcie(x)	dev_get_drvdata((x)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 				       bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	val = readl(priv->base + PCL_APP_READY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		val |= PCL_APP_LTSSM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		val &= ~PCL_APP_LTSSM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	writel(val, priv->base + PCL_APP_READY_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* set RC MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	val = readl(priv->base + PCL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	val |= PCL_MODE_REGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	val &= ~PCL_MODE_REGVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	writel(val, priv->base + PCL_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/* use auxiliary power detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	val = readl(priv->base + PCL_APP_PM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	val |= PCL_SYS_AUX_PWR_DET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	writel(val, priv->base + PCL_APP_PM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	/* assert PERST# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	val = readl(priv->base + PCL_PINCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		 | PCL_PERST_PLDN_REGVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		| PCL_PERST_PLDN_REGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	writel(val, priv->base + PCL_PINCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	uniphier_pcie_ltssm_enable(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	usleep_range(100000, 200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	/* deassert PERST# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	val = readl(priv->base + PCL_PINCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	writel(val, priv->base + PCL_PINCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int uniphier_pcie_wait_rc(struct uniphier_pcie_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* wait PIPE clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	ret = readl_poll_timeout(priv->base + PCL_PIPEMON, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				 status & PCL_PCLK_ALIVE, 100000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		dev_err(priv->pci.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			"Failed to initialize controller in RC mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int uniphier_pcie_link_up(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	val = readl(priv->base + PCL_STATUS_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	mask = PCL_RDLH_LINK_UP | PCL_XMLH_LINK_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return (val & mask) == mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int uniphier_pcie_establish_link(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (dw_pcie_link_up(pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	uniphier_pcie_ltssm_enable(priv, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return dw_pcie_wait_for_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void uniphier_pcie_stop_link(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	uniphier_pcie_ltssm_enable(priv, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void uniphier_pcie_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	raw_spin_lock_irqsave(&pp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	val = readl(priv->base + PCL_RCV_INTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	writel(val, priv->base + PCL_RCV_INTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	raw_spin_unlock_irqrestore(&pp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void uniphier_pcie_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	raw_spin_lock_irqsave(&pp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	val = readl(priv->base + PCL_RCV_INTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	writel(val, priv->base + PCL_RCV_INTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	raw_spin_unlock_irqrestore(&pp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct irq_chip uniphier_pcie_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.name = "PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.irq_mask = uniphier_pcie_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.irq_unmask = uniphier_pcie_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int uniphier_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				  irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	irq_set_chip_and_handler(irq, &uniphier_pcie_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				 handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	irq_set_chip_data(irq, domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct irq_domain_ops uniphier_intx_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.map = uniphier_pcie_intx_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void uniphier_pcie_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct pcie_port *pp = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	u32 val, bit, virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* INT for debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	val = readl(priv->base + PCL_RCV_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (val & PCL_CFG_BW_MGT_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		dev_dbg(pci->dev, "Root Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (val & PCL_CFG_PME_MSI_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		dev_dbg(pci->dev, "PME Interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	writel(val, priv->base + PCL_RCV_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* INTx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	val = readl(priv->base + PCL_RCV_INTX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for_each_set_bit(bit, &reg, PCI_NUM_INTX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		virq = irq_linear_revmap(priv->legacy_irq_domain, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int uniphier_pcie_config_legacy_irq(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct device_node *np = pci->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct device_node *np_intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	np_intc = of_get_child_by_name(np, "legacy-interrupt-controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (!np_intc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		dev_err(pci->dev, "Failed to get legacy-interrupt-controller node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	pp->irq = irq_of_parse_and_map(np_intc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (!pp->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		dev_err(pci->dev, "Failed to get an IRQ entry in legacy-interrupt-controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		goto out_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	priv->legacy_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 						&uniphier_intx_domain_ops, pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (!priv->legacy_irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		dev_err(pci->dev, "Failed to get INTx domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		goto out_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	irq_set_chained_handler_and_data(pp->irq, uniphier_pcie_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 					 pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) out_put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	of_node_put(np_intc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int uniphier_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ret = uniphier_pcie_config_legacy_irq(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	uniphier_pcie_irq_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	dw_pcie_setup_rc(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	ret = uniphier_pcie_establish_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	dw_pcie_msi_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.host_init = uniphier_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 				  struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct dw_pcie *pci = &priv->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	pp->ops = &uniphier_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		if (pp->msi_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			return pp->msi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	ret = dw_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		dev_err(dev, "Failed to initialize host (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int uniphier_pcie_host_enable(struct uniphier_pcie_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	ret = reset_control_deassert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		goto out_clk_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	uniphier_pcie_init_rc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	ret = phy_init(priv->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		goto out_rst_assert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	ret = uniphier_pcie_wait_rc(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		goto out_phy_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) out_phy_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	phy_exit(priv->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) out_rst_assert:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	reset_control_assert(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) out_clk_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct dw_pcie_ops dw_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	.start_link = uniphier_pcie_establish_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	.stop_link = uniphier_pcie_stop_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	.link_up = uniphier_pcie_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int uniphier_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	struct uniphier_pcie_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	priv->pci.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	priv->pci.ops = &dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	priv->pci.dbi_base = devm_pci_remap_cfg_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	if (IS_ERR(priv->pci.dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		return PTR_ERR(priv->pci.dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	priv->base = devm_platform_ioremap_resource_byname(pdev, "link");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	priv->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	priv->rst = devm_reset_control_get_shared(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	if (IS_ERR(priv->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		return PTR_ERR(priv->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	priv->phy = devm_phy_optional_get(dev, "pcie-phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	if (IS_ERR(priv->phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		return PTR_ERR(priv->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	ret = uniphier_pcie_host_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	return uniphier_add_pcie_port(priv, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct of_device_id uniphier_pcie_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	{ .compatible = "socionext,uniphier-pcie", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct platform_driver uniphier_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	.probe  = uniphier_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		.name = "uniphier-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.of_match_table = uniphier_pcie_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) builtin_platform_driver(uniphier_pcie_driver);