Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * SPEAr13xx PCIe Glue Layer Source Code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2010-2014 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Pratyush Anand <pratyush.anand@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Mohit Kumar <mohit.kumar.dhaka@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) struct spear13xx_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct dw_pcie		*pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	void __iomem		*app_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	struct phy		*phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct pcie_app_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32	app_ctrl_0;		/* cr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32	app_ctrl_1;		/* cr1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32	app_status_0;		/* cr2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32	app_status_1;		/* cr3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32	msg_status;		/* cr4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u32	msg_payload;		/* cr5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32	int_sts;		/* cr6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u32	int_clr;		/* cr7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u32	int_mask;		/* cr8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u32	mst_bmisc;		/* cr9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32	phy_ctrl;		/* cr10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u32	phy_status;		/* cr11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u32	cxpl_debug_info_0;	/* cr12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u32	cxpl_debug_info_1;	/* cr13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u32	ven_msg_ctrl_0;		/* cr14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32	ven_msg_ctrl_1;		/* cr15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u32	ven_msg_data_0;		/* cr16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u32	ven_msg_data_1;		/* cr17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u32	ven_msi_0;		/* cr18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32	ven_msi_1;		/* cr19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u32	mst_rmisc;		/* cr20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* CR0 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define APP_LTSSM_ENABLE_ID			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DEVICE_TYPE_RC				(4 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MISCTRL_EN_ID				30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define REG_TRANSLATION_ENABLE			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) /* CR3 ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define XMLH_LINK_UP				(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* CR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MSI_CTRL_INT				(1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define to_spear13xx_pcie(x)	dev_get_drvdata((x)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct dw_pcie *pci = spear13xx_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (dw_pcie_link_up(pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		dev_err(pci->dev, "link already up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	dw_pcie_setup_rc(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * this controller support only 128 bytes read size, however its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * default value in capability register is 512 bytes. So force
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 * it to 128 here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	val = dw_pcie_readw_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	val &= ~PCI_EXP_DEVCTL_READRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	dw_pcie_writew_dbi(pci, exp_cap_off + PCI_EXP_DEVCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, 0x104A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, 0xCD80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	/* enable ltssm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			| (1 << APP_LTSSM_ENABLE_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			| ((u32)1 << REG_TRANSLATION_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			&app_reg->app_ctrl_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return dw_pcie_wait_for_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct spear13xx_pcie *spear13xx_pcie = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct dw_pcie *pci = spear13xx_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	status = readl(&app_reg->int_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (status & MSI_CTRL_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		dw_handle_msi_irq(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	writel(status, &app_reg->int_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct dw_pcie *pci = spear13xx_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* Enable MSI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		dw_pcie_msi_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		writel(readl(&app_reg->int_mask) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				MSI_CTRL_INT, &app_reg->int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int spear13xx_pcie_link_up(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int spear13xx_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	spear13xx_pcie_establish_link(spear13xx_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	spear13xx_pcie_enable_interrupts(spear13xx_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct dw_pcie_host_ops spear13xx_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.host_init = spear13xx_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				   struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	struct dw_pcie *pci = spear13xx_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	pp->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (pp->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		return pp->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			       IRQF_SHARED | IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			       "spear1340-pcie", spear13xx_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		dev_err(dev, "failed to request irq %d\n", pp->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	pp->ops = &spear13xx_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ret = dw_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		dev_err(dev, "failed to initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct dw_pcie_ops dw_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.link_up = spear13xx_pcie_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int spear13xx_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct spear13xx_pcie *spear13xx_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	struct resource *dbi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (!spear13xx_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	pci->ops = &dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	spear13xx_pcie->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (IS_ERR(spear13xx_pcie->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		ret = PTR_ERR(spear13xx_pcie->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		if (ret == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			dev_info(dev, "probe deferred\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			dev_err(dev, "couldn't get pcie-phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	phy_init(spear13xx_pcie->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	spear13xx_pcie->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (IS_ERR(spear13xx_pcie->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		dev_err(dev, "couldn't get clk for pcie\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return PTR_ERR(spear13xx_pcie->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	ret = clk_prepare_enable(spear13xx_pcie->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		dev_err(dev, "couldn't enable clk for pcie\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (IS_ERR(pci->dbi_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		ret = PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		goto fail_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (of_property_read_bool(np, "st,pcie-is-gen1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		pci->link_gen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	platform_set_drvdata(pdev, spear13xx_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		goto fail_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) fail_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	clk_disable_unprepare(spear13xx_pcie->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct of_device_id spear13xx_pcie_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	{ .compatible = "st,spear1340-pcie", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct platform_driver spear13xx_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.probe		= spear13xx_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.name	= "spear-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) builtin_platform_driver(spear13xx_pcie_driver);