Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PCIe host controller driver for Kirin Phone SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *		https://www.huawei.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Xiaowei Song <songxiaowei@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/pci_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REF_CLK_FREQ			100000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* PCIe ELBI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SOC_PCIECTRL_CTRL0_ADDR		0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SOC_PCIECTRL_CTRL1_ADDR		0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SOC_PCIEPHY_CTRL2_ADDR		0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SOC_PCIEPHY_CTRL3_ADDR		0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PCIE_ELBI_SLV_DBI_ENABLE	(0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* info located in APB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PCIE_APP_LTSSM_ENABLE	0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PCIE_APB_PHY_CTRL0	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PCIE_APB_PHY_CTRL1	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PCIE_APB_PHY_STATUS0	0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PCIE_LINKUP_ENABLE	(0x8020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PCIE_LTSSM_ENABLE_BIT	(0x1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PIPE_CLK_STABLE		(0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PHY_REF_PAD_BIT		(0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PHY_PWR_DOWN_BIT	(0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PHY_RST_ACK_BIT		(0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* info located in sysctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SCTRL_PCIE_CMOS_OFFSET	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SCTRL_PCIE_CMOS_BIT	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SCTRL_PCIE_ISO_OFFSET	0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SCTRL_PCIE_ISO_BIT	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SCTRL_PCIE_HPCLK_OFFSET	0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SCTRL_PCIE_HPCLK_BIT	0x184000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SCTRL_PCIE_OE_OFFSET	0x14a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PCIE_DEBOUNCE_PARAM	0xF0F400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PCIE_OE_BYPASS		(0x3 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* peri_crg ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CRGCTRL_PCIE_ASSERT_OFFSET	0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CRGCTRL_PCIE_ASSERT_BIT		0x8c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Time for delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define REF_2_PERST_MIN		20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define REF_2_PERST_MAX		25000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PERST_2_ACCESS_MIN	10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PERST_2_ACCESS_MAX	12000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define LINK_WAIT_MIN		900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define LINK_WAIT_MAX		1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PIPE_CLK_WAIT_MIN	550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PIPE_CLK_WAIT_MAX	600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define TIME_CMOS_MIN		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define TIME_CMOS_MAX		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define TIME_PHY_PD_MIN		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define TIME_PHY_PD_MAX		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) struct kirin_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct dw_pcie	*pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	void __iomem	*apb_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	void __iomem	*phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct regmap	*crgctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct regmap	*sysctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct clk	*apb_sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct clk	*apb_phy_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct clk	*phy_ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct clk	*pcie_aclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct clk	*pcie_aux_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	int		gpio_id_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /* Registers in PCIeCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 					 u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	writel(val, kirin_pcie->apb_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return readl(kirin_pcie->apb_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Registers in PCIePHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 					u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	writel(val, kirin_pcie->phy_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	return readl(kirin_pcie->phy_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			       struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	kirin_pcie->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (IS_ERR(kirin_pcie->phy_ref_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return PTR_ERR(kirin_pcie->phy_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	kirin_pcie->pcie_aux_clk = devm_clk_get(dev, "pcie_aux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (IS_ERR(kirin_pcie->pcie_aux_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return PTR_ERR(kirin_pcie->pcie_aux_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	kirin_pcie->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (IS_ERR(kirin_pcie->apb_phy_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return PTR_ERR(kirin_pcie->apb_phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	kirin_pcie->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (IS_ERR(kirin_pcie->apb_sys_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return PTR_ERR(kirin_pcie->apb_sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	kirin_pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (IS_ERR(kirin_pcie->pcie_aclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return PTR_ERR(kirin_pcie->pcie_aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				    struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	kirin_pcie->apb_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		devm_platform_ioremap_resource_byname(pdev, "apb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (IS_ERR(kirin_pcie->apb_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return PTR_ERR(kirin_pcie->apb_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	kirin_pcie->phy_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		devm_platform_ioremap_resource_byname(pdev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (IS_ERR(kirin_pcie->phy_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		return PTR_ERR(kirin_pcie->phy_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	kirin_pcie->pci->dbi_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		devm_platform_ioremap_resource_byname(pdev, "dbi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (IS_ERR(kirin_pcie->pci->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		return PTR_ERR(kirin_pcie->pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	kirin_pcie->crgctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (IS_ERR(kirin_pcie->crgctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		return PTR_ERR(kirin_pcie->crgctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	kirin_pcie->sysctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (IS_ERR(kirin_pcie->sysctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return PTR_ERR(kirin_pcie->sysctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct device *dev = kirin_pcie->pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	reg_val &= ~PHY_REF_PAD_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	reg_val &= ~PHY_PWR_DOWN_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	reg_val &= ~PHY_RST_ACK_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (reg_val & PIPE_CLK_STABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		dev_err(dev, "PIPE clk is not stable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	val |= PCIE_DEBOUNCE_PARAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	val &= ~PCIE_OE_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		goto close_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		goto apb_sys_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		goto apb_phy_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		goto aclk_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		goto aux_clk_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) close_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) aux_clk_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	clk_disable_unprepare(kirin_pcie->pcie_aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) aclk_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	clk_disable_unprepare(kirin_pcie->apb_phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) apb_phy_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	clk_disable_unprepare(kirin_pcie->apb_sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) apb_sys_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	clk_disable_unprepare(kirin_pcie->phy_ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* Power supply for Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	regmap_write(kirin_pcie->sysctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		     SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	kirin_pcie_oe_enable(kirin_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	regmap_write(kirin_pcie->sysctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		     SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	regmap_write(kirin_pcie->crgctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		     CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	regmap_write(kirin_pcie->sysctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		     SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ret = kirin_pcie_phy_init(kirin_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		goto close_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	/* perst assert Endpoint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			goto close_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) close_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	kirin_pcie_clk_ctrl(kirin_pcie, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 					   bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		val = val | PCIE_ELBI_SLV_DBI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 					   bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		val = val | PCIE_ELBI_SLV_DBI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 				  int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (PCI_SLOT(devfn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		*val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	*val = dw_pcie_read_dbi(pci, where, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 				  int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (PCI_SLOT(devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	dw_pcie_write_dbi(pci, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct pci_ops kirin_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.read = kirin_pcie_rd_own_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.write = kirin_pcie_wr_own_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			       u32 reg, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	dw_pcie_read(base + reg, size, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 				 u32 reg, size_t size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	dw_pcie_write(base + reg, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int kirin_pcie_link_up(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int kirin_pcie_establish_link(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	struct device *dev = kirin_pcie->pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (kirin_pcie_link_up(pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	dw_pcie_setup_rc(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	/* assert LTSSM enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			      PCIE_APP_LTSSM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	/* check if the link is up or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	while (!kirin_pcie_link_up(pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		if (count == 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 			dev_err(dev, "Link Fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int kirin_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	pp->bridge->ops = &kirin_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	kirin_pcie_establish_link(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	dw_pcie_msi_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct dw_pcie_ops kirin_dw_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.read_dbi = kirin_pcie_read_dbi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.write_dbi = kirin_pcie_write_dbi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.link_up = kirin_pcie_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct dw_pcie_host_ops kirin_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	.host_init = kirin_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int kirin_pcie_add_msi(struct dw_pcie *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 				struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 			return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		pci->pp.msi_irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int kirin_add_pcie_port(struct dw_pcie *pci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 			       struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	ret = kirin_pcie_add_msi(pci, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	pci->pp.ops = &kirin_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	return dw_pcie_host_init(&pci->pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int kirin_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	struct kirin_pcie *kirin_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	if (!dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		dev_err(dev, "NULL node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	kirin_pcie = devm_kzalloc(dev, sizeof(struct kirin_pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	if (!kirin_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	pci->ops = &kirin_dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	kirin_pcie->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	ret = kirin_pcie_get_clk(kirin_pcie, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	ret = kirin_pcie_get_resource(kirin_pcie, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 						      "reset-gpios", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	if (kirin_pcie->gpio_id_reset == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	} else if (!gpio_is_valid(kirin_pcie->gpio_id_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		dev_err(dev, "unable to get a valid gpio pin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	ret = kirin_pcie_power_on(kirin_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	platform_set_drvdata(pdev, kirin_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	return kirin_add_pcie_port(pci, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const struct of_device_id kirin_pcie_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	{ .compatible = "hisilicon,kirin960-pcie" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static struct platform_driver kirin_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	.probe			= kirin_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	.driver			= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 		.name			= "kirin-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 		.of_match_table = kirin_pcie_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		.suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) builtin_platform_driver(kirin_pcie_driver);