^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe host controller driver for Intel Gateway SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "../../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PORT_AFR_N_FTS_GEN3 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PORT_AFR_N_FTS_GEN4 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* PCIe Application logic Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCIE_APP_CCR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCIE_APP_CCR_LTSSM_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCIE_APP_MSG_CR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCIE_APP_MSG_XMT_PM_TURNOFF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCIE_APP_PMC 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCIE_APP_PMC_IN_L2 BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCIE_APP_IRNEN 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCIE_APP_IRNCR 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCIE_APP_IRN_AER_REPORT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCIE_APP_IRN_PME BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCIE_APP_IRN_RX_VDM_MSG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCIE_APP_IRN_PM_TO_ACK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCIE_APP_IRN_LINK_AUTO_BW_STAT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCIE_APP_IRN_BW_MGT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCIE_APP_IRN_INTA BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCIE_APP_IRN_INTB BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCIE_APP_IRN_INTC BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCIE_APP_IRN_INTD BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCIE_APP_IRN_MSG_LTR BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCIE_APP_IRN_SYS_ERR_RC BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCIE_APP_INTX_OFST 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCIE_APP_IRN_INT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (PCIE_APP_IRN_AER_REPORT | PCIE_APP_IRN_PME | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PCIE_APP_IRN_RX_VDM_MSG | PCIE_APP_IRN_SYS_ERR_RC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PCIE_APP_IRN_PM_TO_ACK | PCIE_APP_IRN_MSG_LTR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PCIE_APP_IRN_BW_MGT | PCIE_APP_IRN_LINK_AUTO_BW_STAT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PCIE_APP_IRN_INTA | PCIE_APP_IRN_INTB | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PCIE_APP_IRN_INTC | PCIE_APP_IRN_INTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BUS_IATU_OFFSET SZ_256M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RESET_INTERVAL_MS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct intel_pcie_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int pcie_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned int pcie_atu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 num_viewport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct intel_pcie_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct dw_pcie pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *app_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 rst_intrvl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk *core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct reset_control *core_rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void pcie_update_bits(void __iomem *base, u32 ofs, u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) old = readl(base + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val = (old & ~mask) | (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (val != old)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writel(val, base + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline u32 pcie_app_rd(struct intel_pcie_port *lpp, u32 ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return readl(lpp->app_base + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline void pcie_app_wr(struct intel_pcie_port *lpp, u32 ofs, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel(val, lpp->app_base + ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void pcie_app_wr_mask(struct intel_pcie_port *lpp, u32 ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pcie_update_bits(lpp->app_base, ofs, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline u32 pcie_rc_cfg_rd(struct intel_pcie_port *lpp, u32 ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return dw_pcie_readl_dbi(&lpp->pci, ofs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline void pcie_rc_cfg_wr(struct intel_pcie_port *lpp, u32 ofs, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dw_pcie_writel_dbi(&lpp->pci, ofs, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void pcie_rc_cfg_wr_mask(struct intel_pcie_port *lpp, u32 ofs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 mask, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pcie_update_bits(lpp->pci.dbi_base, ofs, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void intel_pcie_ltssm_enable(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pcie_app_wr_mask(lpp, PCIE_APP_CCR, PCIE_APP_CCR_LTSSM_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PCIE_APP_CCR_LTSSM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void intel_pcie_ltssm_disable(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pcie_app_wr_mask(lpp, PCIE_APP_CCR, PCIE_APP_CCR_LTSSM_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void intel_pcie_link_setup(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 offset = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) val = pcie_rc_cfg_rd(lpp, offset + PCI_EXP_LNKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val &= ~(PCI_EXP_LNKCTL_LD | PCI_EXP_LNKCTL_ASPMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pcie_rc_cfg_wr(lpp, offset + PCI_EXP_LNKCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void intel_pcie_init_n_fts(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) switch (pci->link_gen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pci->n_fts[1] = PORT_AFR_N_FTS_GEN3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pci->n_fts[1] = PORT_AFR_N_FTS_GEN4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pci->n_fts[1] = PORT_AFR_N_FTS_GEN12_DFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pci->n_fts[0] = PORT_AFR_N_FTS_GEN12_DFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void intel_pcie_rc_setup(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) intel_pcie_ltssm_disable(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) intel_pcie_link_setup(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) intel_pcie_init_n_fts(&lpp->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dw_pcie_setup_rc(&lpp->pci.pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dw_pcie_upconfig_setup(&lpp->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int intel_pcie_ep_rst_init(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct device *dev = lpp->pci.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) lpp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (IS_ERR(lpp->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ret = PTR_ERR(lpp->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_err(dev, "Failed to request PCIe GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Make initial reset last for 100us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void intel_pcie_core_rst_assert(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) reset_control_assert(lpp->core_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void intel_pcie_core_rst_deassert(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * One micro-second delay to make sure the reset pulse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * wide enough so that core reset is clean.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) reset_control_deassert(lpp->core_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Some SoC core reset also reset PHY, more delay needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * to make sure the reset process is done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void intel_pcie_device_rst_assert(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) gpiod_set_value_cansleep(lpp->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void intel_pcie_device_rst_deassert(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) msleep(lpp->rst_intrvl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) gpiod_set_value_cansleep(lpp->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int intel_pcie_app_logic_setup(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) intel_pcie_device_rst_deassert(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) intel_pcie_ltssm_enable(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return dw_pcie_wait_for_link(&lpp->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void intel_pcie_core_irq_disable(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pcie_app_wr(lpp, PCIE_APP_IRNEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pcie_app_wr(lpp, PCIE_APP_IRNCR, PCIE_APP_IRN_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int intel_pcie_get_resources(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct intel_pcie_port *lpp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct dw_pcie *pci = &lpp->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (IS_ERR(pci->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) lpp->core_clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (IS_ERR(lpp->core_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = PTR_ERR(lpp->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(dev, "Failed to get clks: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) lpp->core_rst = devm_reset_control_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (IS_ERR(lpp->core_rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = PTR_ERR(lpp->core_rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dev_err(dev, "Failed to get resets: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = device_property_read_u32(dev, "reset-assert-ms",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) &lpp->rst_intrvl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) lpp->rst_intrvl = RESET_INTERVAL_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) lpp->app_base = devm_platform_ioremap_resource_byname(pdev, "app");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (IS_ERR(lpp->app_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return PTR_ERR(lpp->app_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) lpp->phy = devm_phy_get(dev, "pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (IS_ERR(lpp->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = PTR_ERR(lpp->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_err(dev, "Couldn't get pcie-phy: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void intel_pcie_deinit_phy(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) phy_exit(lpp->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int intel_pcie_wait_l2(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct dw_pcie *pci = &lpp->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (pci->link_gen < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Send PME_TURN_OFF message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pcie_app_wr_mask(lpp, PCIE_APP_MSG_CR, PCIE_APP_MSG_XMT_PM_TURNOFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PCIE_APP_MSG_XMT_PM_TURNOFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Read PMC status and wait for falling into L2 link state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = readl_poll_timeout(lpp->app_base + PCIE_APP_PMC, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) value & PCIE_APP_PMC_IN_L2, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) jiffies_to_usecs(5 * HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(lpp->pci.dev, "PCIe link enter L2 timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void intel_pcie_turn_off(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (dw_pcie_link_up(&lpp->pci))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) intel_pcie_wait_l2(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Put endpoint device in reset state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) intel_pcie_device_rst_assert(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) pcie_rc_cfg_wr_mask(lpp, PCI_COMMAND, PCI_COMMAND_MEMORY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int intel_pcie_host_setup(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) intel_pcie_core_rst_assert(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) intel_pcie_device_rst_assert(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = phy_init(lpp->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) intel_pcie_core_rst_deassert(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ret = clk_prepare_enable(lpp->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_err(lpp->pci.dev, "Core clock enable failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) intel_pcie_rc_setup(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = intel_pcie_app_logic_setup(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto app_init_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Enable integrated interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pcie_app_wr_mask(lpp, PCIE_APP_IRNEN, PCIE_APP_IRN_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PCIE_APP_IRN_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) app_init_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) clk_disable_unprepare(lpp->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) clk_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) intel_pcie_core_rst_assert(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) intel_pcie_deinit_phy(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void __intel_pcie_remove(struct intel_pcie_port *lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) intel_pcie_core_irq_disable(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) intel_pcie_turn_off(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) clk_disable_unprepare(lpp->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) intel_pcie_core_rst_assert(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) intel_pcie_deinit_phy(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static int intel_pcie_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct intel_pcie_port *lpp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct pcie_port *pp = &lpp->pci.pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dw_pcie_host_deinit(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __intel_pcie_remove(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int __maybe_unused intel_pcie_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct intel_pcie_port *lpp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) intel_pcie_core_irq_disable(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = intel_pcie_wait_l2(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) intel_pcie_deinit_phy(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) clk_disable_unprepare(lpp->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int __maybe_unused intel_pcie_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct intel_pcie_port *lpp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return intel_pcie_host_setup(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int intel_pcie_rc_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct intel_pcie_port *lpp = dev_get_drvdata(pci->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return intel_pcie_host_setup(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Dummy function so that DW core doesn't configure MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int intel_pcie_msi_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static u64 intel_pcie_cpu_addr(struct dw_pcie *pcie, u64 cpu_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return cpu_addr + BUS_IATU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct dw_pcie_ops intel_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .cpu_addr_fixup = intel_pcie_cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const struct dw_pcie_host_ops intel_pcie_dw_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .host_init = intel_pcie_rc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .msi_host_init = intel_pcie_msi_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct intel_pcie_soc pcie_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .pcie_ver = 0x520A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .pcie_atu_offset = 0xC0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .num_viewport = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int intel_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) const struct intel_pcie_soc *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct intel_pcie_port *lpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct pcie_port *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) lpp = devm_kzalloc(dev, sizeof(*lpp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!lpp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) platform_set_drvdata(pdev, lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pci = &lpp->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = intel_pcie_get_resources(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = intel_pcie_ep_rst_init(lpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) data = device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pci->ops = &intel_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pci->version = data->pcie_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pci->atu_base = pci->dbi_base + data->pcie_atu_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pp->ops = &intel_pcie_dw_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = dw_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(dev, "Cannot initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * Intel PCIe doesn't configure IO region, so set viewport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * to not perform IO region access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pci->num_viewport = data->num_viewport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const struct dev_pm_ops intel_pcie_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pcie_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) intel_pcie_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct of_device_id of_intel_pcie_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { .compatible = "intel,lgm-pcie", .data = &pcie_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static struct platform_driver intel_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .probe = intel_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .remove = intel_pcie_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .name = "intel-gw-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .of_match_table = of_intel_pcie_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .pm = &intel_pcie_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) builtin_platform_driver(intel_pcie_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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