^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe host controller driver for HiSilicon STB SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016-2017 HiSilicon Co., Ltd. http://www.hisilicon.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Ruqiang Ju <juruqiang@hisilicon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Jianguo Sun <sunjianguo1@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define to_histb_pcie(x) dev_get_drvdata((x)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCIE_SYS_CTRL0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCIE_SYS_CTRL1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCIE_SYS_CTRL7 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCIE_SYS_CTRL13 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCIE_SYS_CTRL15 0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCIE_SYS_CTRL16 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCIE_SYS_CTRL17 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCIE_SYS_STAT0 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCIE_SYS_STAT4 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCIE_RDLH_LINK_UP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCIE_XMLH_LINK_UP BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCIE_APP_LTSSM_ENABLE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCIE_DEVICE_TYPE_MASK GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCIE_WM_EP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCIE_WM_LEGACY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCIE_WM_RC BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCIE_LTSSM_STATE_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCIE_LTSSM_STATE_ACTIVE 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct histb_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct clk *aux_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct clk *pipe_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct clk *sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct clk *bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct reset_control *soft_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct reset_control *sys_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct reset_control *bus_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void __iomem *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct regulator *vpcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static u32 histb_pcie_readl(struct histb_pcie *histb_pcie, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return readl(histb_pcie->ctrl + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void histb_pcie_writel(struct histb_pcie *histb_pcie, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) writel(val, histb_pcie->ctrl + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void histb_pcie_dbi_w_mode(struct pcie_port *pp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct histb_pcie *hipcie = to_histb_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) val = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) val |= PCIE_ELBI_SLV_DBI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void histb_pcie_dbi_r_mode(struct pcie_port *pp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct histb_pcie *hipcie = to_histb_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) val = histb_pcie_readl(hipcie, PCIE_SYS_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) val |= PCIE_ELBI_SLV_DBI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val &= ~PCIE_ELBI_SLV_DBI_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) histb_pcie_writel(hipcie, PCIE_SYS_CTRL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static u32 histb_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 reg, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) histb_pcie_dbi_r_mode(&pci->pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dw_pcie_read(base + reg, size, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) histb_pcie_dbi_r_mode(&pci->pp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void histb_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 reg, size_t size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) histb_pcie_dbi_w_mode(&pci->pp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dw_pcie_write(base + reg, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) histb_pcie_dbi_w_mode(&pci->pp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int histb_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (PCI_SLOT(devfn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *val = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *val = dw_pcie_read_dbi(pci, where, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int histb_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (PCI_SLOT(devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dw_pcie_write_dbi(pci, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct pci_ops histb_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .read = histb_pcie_rd_own_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .write = histb_pcie_wr_own_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int histb_pcie_link_up(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct histb_pcie *hipcie = to_histb_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) regval = histb_pcie_readl(hipcie, PCIE_SYS_STAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) status = histb_pcie_readl(hipcie, PCIE_SYS_STAT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) status &= PCIE_LTSSM_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if ((regval & PCIE_XMLH_LINK_UP) && (regval & PCIE_RDLH_LINK_UP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) (status == PCIE_LTSSM_STATE_ACTIVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int histb_pcie_establish_link(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct histb_pcie *hipcie = to_histb_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (dw_pcie_link_up(pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_info(pci->dev, "Link already up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* PCIe RC work mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) regval &= ~PCIE_DEVICE_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) regval |= PCIE_WM_RC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) histb_pcie_writel(hipcie, PCIE_SYS_CTRL0, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* setup root complex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) dw_pcie_setup_rc(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* assert LTSSM enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) regval = histb_pcie_readl(hipcie, PCIE_SYS_CTRL7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) regval |= PCIE_APP_LTSSM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) histb_pcie_writel(hipcie, PCIE_SYS_CTRL7, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return dw_pcie_wait_for_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int histb_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pp->bridge->ops = &histb_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) histb_pcie_establish_link(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dw_pcie_msi_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct dw_pcie_host_ops histb_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .host_init = histb_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void histb_pcie_host_disable(struct histb_pcie *hipcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) reset_control_assert(hipcie->soft_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) reset_control_assert(hipcie->sys_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) reset_control_assert(hipcie->bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) clk_disable_unprepare(hipcie->aux_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) clk_disable_unprepare(hipcie->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) clk_disable_unprepare(hipcie->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) clk_disable_unprepare(hipcie->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (gpio_is_valid(hipcie->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) gpio_set_value_cansleep(hipcie->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (hipcie->vpcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) regulator_disable(hipcie->vpcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int histb_pcie_host_enable(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct histb_pcie *hipcie = to_histb_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* power on PCIe device if have */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (hipcie->vpcie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = regulator_enable(hipcie->vpcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_err(dev, "failed to enable regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (gpio_is_valid(hipcie->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) gpio_set_value_cansleep(hipcie->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = clk_prepare_enable(hipcie->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_err(dev, "cannot prepare/enable bus clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) goto err_bus_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = clk_prepare_enable(hipcie->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(dev, "cannot prepare/enable sys clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto err_sys_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = clk_prepare_enable(hipcie->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_err(dev, "cannot prepare/enable pipe clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) goto err_pipe_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = clk_prepare_enable(hipcie->aux_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(dev, "cannot prepare/enable aux clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto err_aux_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) reset_control_assert(hipcie->soft_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) reset_control_deassert(hipcie->soft_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) reset_control_assert(hipcie->sys_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) reset_control_deassert(hipcie->sys_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) reset_control_assert(hipcie->bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) reset_control_deassert(hipcie->bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) err_aux_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) clk_disable_unprepare(hipcie->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) err_pipe_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) clk_disable_unprepare(hipcie->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) err_sys_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) clk_disable_unprepare(hipcie->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) err_bus_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (hipcie->vpcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) regulator_disable(hipcie->vpcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct dw_pcie_ops dw_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .read_dbi = histb_pcie_read_dbi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .write_dbi = histb_pcie_write_dbi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .link_up = histb_pcie_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int histb_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct histb_pcie *hipcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct pcie_port *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) enum of_gpio_flags of_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned long flag = GPIOF_DIR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) hipcie = devm_kzalloc(dev, sizeof(*hipcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (!hipcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) hipcie->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pci->ops = &dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) hipcie->ctrl = devm_platform_ioremap_resource_byname(pdev, "control");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (IS_ERR(hipcie->ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_err(dev, "cannot get control reg base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return PTR_ERR(hipcie->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc-dbi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (IS_ERR(pci->dbi_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_err(dev, "cannot get rc-dbi base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) hipcie->vpcie = devm_regulator_get_optional(dev, "vpcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (IS_ERR(hipcie->vpcie)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (PTR_ERR(hipcie->vpcie) != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return PTR_ERR(hipcie->vpcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) hipcie->vpcie = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) hipcie->reset_gpio = of_get_named_gpio_flags(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "reset-gpios", 0, &of_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (of_flags & OF_GPIO_ACTIVE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) flag |= GPIOF_ACTIVE_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (gpio_is_valid(hipcie->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = devm_gpio_request_one(dev, hipcie->reset_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) flag, "PCIe device power control");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(dev, "unable to request gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) hipcie->aux_clk = devm_clk_get(dev, "aux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (IS_ERR(hipcie->aux_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_err(dev, "Failed to get PCIe aux clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return PTR_ERR(hipcie->aux_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) hipcie->pipe_clk = devm_clk_get(dev, "pipe");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (IS_ERR(hipcie->pipe_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_err(dev, "Failed to get PCIe pipe clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return PTR_ERR(hipcie->pipe_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) hipcie->sys_clk = devm_clk_get(dev, "sys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (IS_ERR(hipcie->sys_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_err(dev, "Failed to get PCIEe sys clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return PTR_ERR(hipcie->sys_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) hipcie->bus_clk = devm_clk_get(dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (IS_ERR(hipcie->bus_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(dev, "Failed to get PCIe bus clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return PTR_ERR(hipcie->bus_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) hipcie->soft_reset = devm_reset_control_get(dev, "soft");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (IS_ERR(hipcie->soft_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_err(dev, "couldn't get soft reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return PTR_ERR(hipcie->soft_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) hipcie->sys_reset = devm_reset_control_get(dev, "sys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (IS_ERR(hipcie->sys_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_err(dev, "couldn't get sys reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return PTR_ERR(hipcie->sys_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) hipcie->bus_reset = devm_reset_control_get(dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (IS_ERR(hipcie->bus_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(dev, "couldn't get bus reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return PTR_ERR(hipcie->bus_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (IS_ENABLED(CONFIG_PCI_MSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pp->msi_irq = platform_get_irq_byname(pdev, "msi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (pp->msi_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return pp->msi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) hipcie->phy = devm_phy_get(dev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (IS_ERR(hipcie->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_info(dev, "no pcie-phy found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) hipcie->phy = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* fall through here!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * if no pcie-phy found, phy init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * should be done under boot!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) phy_init(hipcie->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pp->ops = &histb_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) platform_set_drvdata(pdev, hipcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = histb_pcie_host_enable(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(dev, "failed to enable host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = dw_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dev_err(dev, "failed to initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int histb_pcie_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct histb_pcie *hipcie = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) histb_pcie_host_disable(hipcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (hipcie->phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) phy_exit(hipcie->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct of_device_id histb_pcie_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { .compatible = "hisilicon,hi3798cv200-pcie", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_DEVICE_TABLE(of, histb_pcie_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static struct platform_driver histb_pcie_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .probe = histb_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .remove = histb_pcie_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .name = "histb-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .of_match_table = histb_pcie_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) module_platform_driver(histb_pcie_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MODULE_DESCRIPTION("HiSilicon STB PCIe host controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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