^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe host controller driver for HiSilicon SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 HiSilicon Co., Ltd. http://www.hisilicon.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Zhou Wang <wangzhou1@hisilicon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Dacai Zhu <zhudacai@hisilicon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Gabriele Paoloni <gabriele.paoloni@huawei.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci-acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci-ecam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "../../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #if defined(CONFIG_PCI_HISI) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int hisi_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct pci_config_window *cfg = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int dev = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (bus->number == cfg->busr.start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* access only one slot on each root port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (dev > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return pci_generic_config_read32(bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return pci_generic_config_read(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int hisi_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int where, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct pci_config_window *cfg = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int dev = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (bus->number == cfg->busr.start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* access only one slot on each root port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (dev > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return pci_generic_config_write32(bus, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return pci_generic_config_write(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void __iomem *hisi_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct pci_config_window *cfg = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void __iomem *reg_base = cfg->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (bus->number == cfg->busr.start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return reg_base + where;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return pci_ecam_map_bus(bus, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int hisi_pcie_init(struct pci_config_window *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct device *dev = cfg->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct acpi_device *adev = to_acpi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct acpi_pci_root *root = acpi_driver_data(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Retrieve RC base and size from a HISI0081 device with _UID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * matching our segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = acpi_get_rc_resources(dev, "HISI0081", root->segment, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_err(dev, "can't get rc base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cfg->priv = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const struct pci_ecam_ops hisi_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .bus_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .init = hisi_pcie_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .map_bus = hisi_pcie_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .read = hisi_pcie_rd_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .write = hisi_pcie_wr_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #ifdef CONFIG_PCI_HISI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int hisi_pcie_platform_init(struct pci_config_window *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct device *dev = cfg->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev_err(dev, "missing \"reg[1]\"property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) reg_base = devm_pci_remap_cfgspace(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!reg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) cfg->priv = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct pci_ecam_ops hisi_pcie_platform_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .bus_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .init = hisi_pcie_platform_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .map_bus = hisi_pcie_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .read = hisi_pcie_rd_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .write = hisi_pcie_wr_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct of_device_id hisi_pcie_almost_ecam_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .compatible = "hisilicon,hip06-pcie-ecam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .data = &hisi_pcie_platform_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .compatible = "hisilicon,hip07-pcie-ecam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .data = &hisi_pcie_platform_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static struct platform_driver hisi_pcie_almost_ecam_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .probe = pci_host_common_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .name = "hisi-pcie-almost-ecam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .of_match_table = hisi_pcie_almost_ecam_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) builtin_platform_driver(hisi_pcie_almost_ecam_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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