Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "pcie-dw-dmatest.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "../rockchip-pcie-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static int test_size = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) module_param_named(size,  test_size, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) MODULE_PARM_DESC(size, "each packet size in bytes");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static unsigned int cycles_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) module_param(cycles_count, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) MODULE_PARM_DESC(cycles_count, "how many erase cycles to do (default 1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static unsigned int chn_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) module_param(chn_en, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) MODULE_PARM_DESC(chn_en, "Each bits for one dma channel, up to 2 channels, (default enable channel 0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static unsigned int rw_test = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) module_param(rw_test, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) MODULE_PARM_DESC(rw_test, "Read/Write test, 1-read 2-write 3-both(default 3)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static unsigned int bus_addr = 0x3c000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) module_param(bus_addr, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) MODULE_PARM_DESC(bus_addr, "Dmatest chn0 bus_addr(remote), chn1 add offset 0x100000, (default 0x3c000000)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static unsigned int local_addr = 0x3c000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) module_param(local_addr, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) MODULE_PARM_DESC(local_addr, "Dmatest chn0 local_addr(local), chn1 add offset 0x100000, (default 0x3c000000)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static unsigned int test_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) module_param(test_dev, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) MODULE_PARM_DESC(test_dev, "Choose dma_obj device,(default 0)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PCIE_DW_MISC_DMATEST_DEV_MAX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PCIE_DMA_OFFSET			0x380000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PCIE_DMA_CTRL_OFF		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PCIE_DMA_WR_ENB			0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PCIE_DMA_WR_CTRL_LO		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PCIE_DMA_WR_CTRL_HI		0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define PCIE_DMA_WR_XFERSIZE		0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PCIE_DMA_WR_SAR_PTR_LO		0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PCIE_DMA_WR_SAR_PTR_HI		0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PCIE_DMA_WR_DAR_PTR_LO		0x214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PCIE_DMA_WR_DAR_PTR_HI		0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PCIE_DMA_WR_WEILO		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define PCIE_DMA_WR_WEIHI		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define PCIE_DMA_WR_DOORBELL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PCIE_DMA_WR_INT_STATUS		0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PCIE_DMA_WR_INT_MASK		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PCIE_DMA_WR_INT_CLEAR		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define PCIE_DMA_RD_ENB			0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PCIE_DMA_RD_CTRL_LO		0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define PCIE_DMA_RD_CTRL_HI		0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PCIE_DMA_RD_XFERSIZE		0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PCIE_DMA_RD_SAR_PTR_LO		0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PCIE_DMA_RD_SAR_PTR_HI		0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define PCIE_DMA_RD_DAR_PTR_LO		0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PCIE_DMA_RD_DAR_PTR_HI		0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PCIE_DMA_RD_WEILO		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PCIE_DMA_RD_WEIHI		0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PCIE_DMA_RD_DOORBELL		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define PCIE_DMA_RD_INT_STATUS		0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PCIE_DMA_RD_INT_MASK		0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define PCIE_DMA_RD_INT_CLEAR		0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define PCIE_DMA_CHANEL_MAX_NUM		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) struct pcie_dw_dmatest_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct dma_trx_obj *obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	bool irq_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct completion rd_done[PCIE_DMA_CHANEL_MAX_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct completion wr_done[PCIE_DMA_CHANEL_MAX_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct mutex rd_lock[PCIE_DMA_CHANEL_MAX_NUM];	/* Corresponding to each read DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct mutex wr_lock[PCIE_DMA_CHANEL_MAX_NUM];	/* Corresponding to each write DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static struct pcie_dw_dmatest_dev s_dmatest_dev[PCIE_DW_MISC_DMATEST_DEV_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int cur_dmatest_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void pcie_dw_dmatest_show(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	for (i = 0; i < PCIE_DW_MISC_DMATEST_DEV_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		if (s_dmatest_dev[i].obj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			dev_info(s_dmatest_dev[i].obj->dev, " test_dev index %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	dev_info(s_dmatest_dev[test_dev].obj->dev, " is current test_dev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int rk_pcie_get_dma_status(struct dw_pcie *pci, u8 chn, enum dma_dir dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	union int_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	union int_clear clears;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	dev_dbg(pci->dev, "%s %x %x\n", __func__, dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_INT_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (dir == DMA_TO_BUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		status.asdword = dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		if (status.donesta & BIT(chn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			clears.doneclr = 0x1 << chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_INT_CLEAR, clears.asdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		if (status.abortsta & BIT(chn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			dev_err(pci->dev, "%s, write abort\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			clears.abortclr = 0x1 << chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_WR_INT_CLEAR, clears.asdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		status.asdword = dw_pcie_readl_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		if (status.donesta & BIT(chn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			clears.doneclr = 0x1 << chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_CLEAR, clears.asdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		if (status.abortsta & BIT(chn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			dev_err(pci->dev, "%s, read abort %x\n", __func__, status.asdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			clears.abortclr = 0x1 << chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			dw_pcie_writel_dbi(pci, PCIE_DMA_OFFSET + PCIE_DMA_RD_INT_CLEAR, clears.asdword);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int rk_pcie_dma_wait_for_finised(struct dma_trx_obj *obj, struct dw_pcie *pci, struct dma_table *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		ret = rk_pcie_get_dma_status(pci, table->chn, table->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	} while (!ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int rk_pcie_dma_frombus(struct pcie_dw_dmatest_dev *dmatest_dev, u32 chn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			       u32 local_paddr, u32 bus_paddr, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct dma_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct dma_trx_obj *obj = dmatest_dev->obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct dw_pcie *pci = dmatest_dev->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (chn >= PCIE_DMA_CHANEL_MAX_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	table = kzalloc(sizeof(struct dma_table), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (!table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	mutex_lock(&dmatest_dev->rd_lock[chn]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (dmatest_dev->irq_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		reinit_completion(&dmatest_dev->rd_done[chn]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	table->buf_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	table->bus = bus_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	table->local = local_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	table->chn = chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	table->dir = DMA_FROM_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	obj->config_dma_func(table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	obj->start_dma_func(obj, table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (dmatest_dev->irq_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		ret = wait_for_completion_interruptible_timeout(&dmatest_dev->rd_done[chn], HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			dev_err(obj->dev, "%s interrupted\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		else if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			dev_err(obj->dev, "%s timed out\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		ret = rk_pcie_dma_wait_for_finised(obj, pci, table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	mutex_unlock(&dmatest_dev->rd_lock[chn]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	kfree(table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int rk_pcie_dma_tobus(struct pcie_dw_dmatest_dev *dmatest_dev, u32 chn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			     u32 bus_paddr, u32 local_paddr, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct dma_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct dma_trx_obj *obj = dmatest_dev->obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct dw_pcie *pci = dmatest_dev->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (chn >= PCIE_DMA_CHANEL_MAX_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	table = kzalloc(sizeof(struct dma_table), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (!table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	mutex_lock(&dmatest_dev->wr_lock[chn]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (dmatest_dev->irq_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		reinit_completion(&dmatest_dev->wr_done[chn]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	table->buf_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	table->bus = bus_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	table->local = local_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	table->chn = chn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	table->dir = DMA_TO_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	obj->config_dma_func(table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	obj->start_dma_func(obj, table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (dmatest_dev->irq_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		ret = wait_for_completion_interruptible_timeout(&dmatest_dev->wr_done[chn], HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			dev_err(obj->dev, "%s interrupted\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		else if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			dev_err(obj->dev, "%s timed out\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		ret = rk_pcie_dma_wait_for_finised(obj, pci, table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	mutex_unlock(&dmatest_dev->wr_lock[chn]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	kfree(table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int rk_pcie_dma_interrupt_handler_call_back(struct dma_trx_obj *obj, u32 chn, enum dma_dir dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct pcie_dw_dmatest_dev *dmatest_dev = (struct pcie_dw_dmatest_dev *)obj->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (chn >= PCIE_DMA_CHANEL_MAX_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (dir == DMA_FROM_BUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		complete(&dmatest_dev->rd_done[chn]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		complete(&dmatest_dev->wr_done[chn]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct dma_trx_obj *pcie_dw_dmatest_register(struct dw_pcie *pci, bool irq_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct dma_trx_obj *obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct pcie_dw_dmatest_dev *dmatest_dev = &s_dmatest_dev[cur_dmatest_dev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	obj = devm_kzalloc(pci->dev, sizeof(struct dma_trx_obj), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (!obj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	obj->dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	obj->priv = dmatest_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	obj->cb = rk_pcie_dma_interrupt_handler_call_back;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	/* Save for dmatest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	dmatest_dev->obj = obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	dmatest_dev->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	for (i = 0; i < PCIE_DMA_CHANEL_MAX_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		init_completion(&dmatest_dev->rd_done[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		init_completion(&dmatest_dev->wr_done[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		mutex_init(&dmatest_dev->rd_lock[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		mutex_init(&dmatest_dev->wr_lock[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	/* Enable IRQ transfer as default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	dmatest_dev->irq_en = irq_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	cur_dmatest_dev++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int dma_test(struct pcie_dw_dmatest_dev *dmatest_dev, u32 chn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		    u32 bus_paddr, u32 local_paddr, u32 size, u32 loop, u8 rd_en, u8 wr_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	ktime_t start_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ktime_t end_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	ktime_t cost_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	long long total_byte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	long long us = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct dma_trx_obj *obj = dmatest_dev->obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	start_time = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	for (i = 0; i < loop; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		if (rd_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			rk_pcie_dma_frombus(dmatest_dev, chn, local_paddr, bus_paddr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			dma_sync_single_for_cpu(obj->dev, local_paddr, size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		if (wr_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			dma_sync_single_for_device(obj->dev, local_paddr, size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			rk_pcie_dma_tobus(dmatest_dev, chn, bus_paddr, local_paddr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	end_time = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	cost_time = ktime_sub(end_time, start_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	us = ktime_to_us(cost_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	total_byte = (wr_en + rd_en) * size * loop; /* 1 rd,1 wr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	total_byte = total_byte * (1000000 / 1024) / us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	pr_err("pcie dma %s/%s test (%d+%d)*%d*%d cost %lldus speed:%lldKB/S\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	       wr_en ? "wr" : "", rd_en ? "rd" : "", wr_en, rd_en, size, loop, us, total_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int dma_test_ch0(void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	dma_test(&s_dmatest_dev[test_dev], 0, bus_addr, local_addr, test_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		 cycles_count, rw_test & 0x1, (rw_test & 0x2) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int dma_test_ch1(void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	/* Test in different area with ch0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (chn_en == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		dma_test(&s_dmatest_dev[test_dev], 1, bus_addr + test_size, local_addr + test_size, test_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			 cycles_count, rw_test & 0x1, (rw_test & 0x2) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		dma_test(&s_dmatest_dev[test_dev], 1, bus_addr, local_addr, test_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			 cycles_count, rw_test & 0x1, (rw_test & 0x2) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int dma_run(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (chn_en == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		kthread_run(dma_test_ch0, NULL, "dma_test_ch0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		kthread_run(dma_test_ch1, NULL, "dma_test_ch1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	} else if (chn_en == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		dma_test_ch1(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		dma_test_ch0(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int pcie_dw_dmatest(const char *val, const struct kernel_param *kp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	char tmp[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	if (!s_dmatest_dev[0].obj) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		pr_err("dmatest dev not exits\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		kfree(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	strncpy(tmp, val, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (!strncmp(tmp, "run", 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		dma_run();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	} else if (!strncmp(tmp, "show", 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		pcie_dw_dmatest_show();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		pr_info("input error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const struct kernel_param_ops pcie_dw_dmatest_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.set = pcie_dw_dmatest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	.get = param_get_uint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) module_param_cb(dmatest, &pcie_dw_dmatest_ops, &pcie_dw_dmatest, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MODULE_PARM_DESC(dmatest, "test rockchip pcie dma module");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_AUTHOR("Jon Lin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MODULE_LICENSE("GPL");