^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Synopsys DesignWare PCIe host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * https://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Jingoo Han <jg1.han@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _PCIE_DESIGNWARE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _PCIE_DESIGNWARE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci-epc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci-epf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Parameters for the waiting for link up routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LINK_WAIT_MAX_RETRIES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LINK_WAIT_USLEEP_MIN 90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LINK_WAIT_USLEEP_MAX 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Parameters for the waiting for iATU enabled routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LINK_WAIT_MAX_IATU_RETRIES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LINK_WAIT_IATU 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Synopsys-specific PCIe configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCIE_PORT_AFR 0x70C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PORT_AFR_N_FTS_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PORT_AFR_CC_N_FTS(n) FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PORT_AFR_ENTER_ASPM BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCIE_PORT_LINK_CONTROL 0x710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PORT_LINK_LPBK_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PORT_LINK_DLL_LINK_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PORT_LINK_FAST_LINK_MODE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PORT_LINK_MODE_MASK GENMASK(21, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCIE_PORT_DEBUG0 0x728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PORT_LOGIC_LTSSM_STATE_L0 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCIE_PORT_DEBUG1 0x72C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PORT_LOGIC_SPEED_CHANGE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCIE_MSI_ADDR_LO 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCIE_MSI_ADDR_HI 0x824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCIE_MSI_INTR0_ENABLE 0x828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCIE_MSI_INTR0_MASK 0x82C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCIE_MSI_INTR0_STATUS 0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PORT_MLTI_UPCFG_SUPPORT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCIE_ATU_VIEWPORT 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCIE_ATU_REGION_INBOUND BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCIE_ATU_REGION_OUTBOUND 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCIE_ATU_CR1 0x904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCIE_ATU_TYPE_MEM 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCIE_ATU_TYPE_IO 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCIE_ATU_TYPE_CFG0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCIE_ATU_TYPE_CFG1 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PCIE_ATU_CR2 0x908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PCIE_ATU_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PCIE_ATU_LOWER_BASE 0x90C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCIE_ATU_UPPER_BASE 0x910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCIE_ATU_LIMIT 0x914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCIE_ATU_LOWER_TARGET 0x918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCIE_ATU_UPPER_TARGET 0x91C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCIE_MISC_CONTROL_1_OFF 0x8BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCIE_DBI_RO_WR_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCIE_MSIX_DOORBELL 0x948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCIE_MSIX_DOORBELL_PF_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCIE_PL_CHK_REG_CHK_REG_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCIE_PL_CHK_REG_ERR_ADDR 0xB28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * iATU Unroll-specific register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * From 4.80 core version the address translation will be made by unroll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PCIE_ATU_UNR_REGION_CTRL1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCIE_ATU_UNR_REGION_CTRL2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCIE_ATU_UNR_LOWER_BASE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCIE_ATU_UNR_UPPER_BASE 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCIE_ATU_UNR_LOWER_LIMIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCIE_ATU_UNR_LOWER_TARGET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCIE_ATU_UNR_UPPER_TARGET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCIE_ATU_UNR_UPPER_LIMIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * The default address offset between dbi_base and atu_base. Root controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * drivers are not required to initialize atu_base if the offset matches this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * default; the driver core automatically derives atu_base from dbi_base using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * this offset, if atu_base not set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DEFAULT_DBI_ATU_OFFSET (0x3 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Register address builder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ((region) << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) (((region) << 9) | BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MAX_MSI_IRQS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MAX_MSI_IRQS_PER_CTRL 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MSI_REG_CTRL_BLOCK_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MSI_DEF_NUM_VECTORS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Maximum number of inbound/outbound iATUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MAX_IATU_IN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MAX_IATU_OUT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct pcie_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct dw_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct dw_pcie_ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) enum dw_pcie_region_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DW_PCIE_REGION_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DW_PCIE_REGION_INBOUND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DW_PCIE_REGION_OUTBOUND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) enum dw_pcie_device_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DW_PCIE_UNKNOWN_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) DW_PCIE_EP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DW_PCIE_LEG_EP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DW_PCIE_RC_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct dw_pcie_host_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int (*host_init)(struct pcie_port *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void (*set_num_vectors)(struct pcie_port *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int (*msi_host_init)(struct pcie_port *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct pcie_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u64 cfg0_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void __iomem *va_cfg0_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 cfg0_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) resource_size_t io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) phys_addr_t io_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const struct dw_pcie_host_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int msi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct irq_domain *msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u16 msi_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dma_addr_t msi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct irq_chip *msi_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 num_vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 irq_mask[MAX_MSI_CTRLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) enum dw_pcie_as_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) DW_PCIE_AS_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DW_PCIE_AS_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DW_PCIE_AS_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct dw_pcie_ep_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) void (*ep_init)(struct dw_pcie_ep *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) enum pci_epc_irq_type type, u16 interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Provide a method to implement the different func config space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * access for different platform, if different func have different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * offset, return the offset of func. if use write a register way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * return a 0, and implement code in callback function of platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct dw_pcie_ep_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 func_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 msi_cap; /* MSI capability offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u8 msix_cap; /* MSI-X capability offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct dw_pcie_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct pci_epc *epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct list_head func_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) const struct dw_pcie_ep_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) phys_addr_t phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) size_t addr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) size_t page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 bar_to_atu[PCI_STD_NUM_BARS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) phys_addr_t *outbound_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long *ib_window_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long *ob_window_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 num_ib_windows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 num_ob_windows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void __iomem *msi_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) phys_addr_t msi_mem_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct dw_pcie_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u64 (*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) size_t size, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) size_t size, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int (*link_up)(struct dw_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int (*start_link)(struct dw_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) void (*stop_link)(struct dw_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct dw_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void __iomem *dbi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void __iomem *dbi_base2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Used when iatu_unroll_enabled is true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void __iomem *atu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 num_viewport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct pcie_port pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct dw_pcie_ep ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) const struct dw_pcie_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int link_gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u8 n_fts[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bool iatu_unroll_enabled: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) bool io_cfg_atu_shared: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define to_dw_pcie_from_ep(endpoint) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) container_of((endpoint), struct dw_pcie, ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int dw_pcie_read(void __iomem *addr, int size, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int dw_pcie_write(void __iomem *addr, int size, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int dw_pcie_link_up(struct dw_pcie *pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void dw_pcie_upconfig_setup(struct dw_pcie *pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int dw_pcie_wait_for_link(struct dw_pcie *pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int type, u64 cpu_addr, u64 pci_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int type, u64 cpu_addr, u64 pci_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int bar, u64 cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) enum dw_pcie_as_type as_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) enum dw_pcie_region_type type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void dw_pcie_setup(struct dw_pcie *pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dw_pcie_write_dbi(pci, reg, 0x4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return dw_pcie_read_dbi(pci, reg, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dw_pcie_write_dbi(pci, reg, 0x2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return dw_pcie_read_dbi(pci, reg, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dw_pcie_write_dbi(pci, reg, 0x1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return dw_pcie_read_dbi(pci, reg, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dw_pcie_write_dbi2(pci, reg, 0x4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) reg = PCIE_MISC_CONTROL_1_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) val = dw_pcie_readl_dbi(pci, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) val |= PCIE_DBI_RO_WR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dw_pcie_writel_dbi(pci, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) reg = PCIE_MISC_CONTROL_1_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) val = dw_pcie_readl_dbi(pci, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) val &= ~PCIE_DBI_RO_WR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dw_pcie_writel_dbi(pci, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #ifdef CONFIG_PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void dw_pcie_msi_init(struct pcie_port *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) void dw_pcie_free_msi(struct pcie_port *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) void dw_pcie_setup_rc(struct pcie_port *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int dw_pcie_host_init(struct pcie_port *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) void dw_pcie_host_deinit(struct pcie_port *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int dw_pcie_allocate_domains(struct pcie_port *pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static inline void dw_pcie_msi_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static inline void dw_pcie_free_msi(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static inline void dw_pcie_setup_rc(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static inline int dw_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static inline void dw_pcie_host_deinit(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static inline int dw_pcie_allocate_domains(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #ifdef CONFIG_PCIE_DW_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int dw_pcie_ep_init(struct dw_pcie_ep *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u8 interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u16 interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u16 interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct dw_pcie_ep_func *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static inline int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static inline void dw_pcie_ep_init_notify(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u8 interrupt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u16 interrupt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u16 interrupt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static inline struct dw_pcie_ep_func *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #endif /* _PCIE_DESIGNWARE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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