^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Synopsys DesignWare PCIe host controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * https://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Jingoo Han <jg1.han@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "../../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * These interfaces resemble the pci_find_*capability() interfaces, but these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * are for configuring host controllers, which are bridges *to* PCI devices but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * are not PCI devices themselves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u8 cap_id, next_cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (!cap_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) reg = dw_pcie_readw_dbi(pci, cap_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) cap_id = (reg & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (cap_id > PCI_CAP_ID_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (cap_id == cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) next_cap_ptr = (reg & 0xff00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 next_cap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) next_cap_ptr = (reg & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int ttl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int pos = PCI_CFG_SPACE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* minimum 8 bytes per capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pos = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) header = dw_pcie_readl_dbi(pci, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * If we have no capabilities, this is indicated by cap ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * cap version and next pointer all being 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (header == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) while (ttl-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (PCI_EXT_CAP_ID(header) == cap && pos != start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pos = PCI_EXT_CAP_NEXT(header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (pos < PCI_CFG_SPACE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) header = dw_pcie_readl_dbi(pci, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return dw_pcie_find_next_ext_capability(pci, 0, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int dw_pcie_read(void __iomem *addr, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!IS_ALIGNED((uintptr_t)addr, size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (size == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *val = readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } else if (size == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *val = readw(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } else if (size == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *val = readb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) EXPORT_SYMBOL_GPL(dw_pcie_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int dw_pcie_write(void __iomem *addr, int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!IS_ALIGNED((uintptr_t)addr, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) else if (size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) writew(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) else if (size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writeb(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return PCIBIOS_BAD_REGISTER_NUMBER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) EXPORT_SYMBOL_GPL(dw_pcie_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (pci->ops->read_dbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return pci->ops->read_dbi(pci, pci->dbi_base, reg, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = dw_pcie_read(pci->dbi_base + reg, size, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_err(pci->dev, "Read DBI address failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EXPORT_SYMBOL_GPL(dw_pcie_read_dbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (pci->ops->write_dbi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pci->ops->write_dbi(pci, pci->dbi_base, reg, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = dw_pcie_write(pci->dbi_base + reg, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_err(pci->dev, "Write DBI address failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) EXPORT_SYMBOL_GPL(dw_pcie_write_dbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (pci->ops->write_dbi2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pci->ops->write_dbi2(pci, pci->dbi_base2, reg, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_err(pci->dev, "write DBI address failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (pci->ops->read_dbi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return pci->ops->read_dbi(pci, pci->atu_base, reg, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = dw_pcie_read(pci->atu_base + reg, 4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_err(pci->dev, "Read ATU address failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (pci->ops->write_dbi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pci->ops->write_dbi(pci, pci->atu_base, reg, 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = dw_pcie_write(pci->atu_base + reg, 4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_err(pci->dev, "Write ATU address failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return dw_pcie_readl_atu(pci, offset + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void dw_pcie_writel_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dw_pcie_writel_atu(pci, offset + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void dw_pcie_prog_outbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int index, int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u64 cpu_addr, u64 pci_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 retries, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u64 limit_addr = cpu_addr + size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) lower_32_bits(cpu_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) upper_32_bits(cpu_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) lower_32_bits(limit_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) upper_32_bits(limit_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) lower_32_bits(pci_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) upper_32_bits(pci_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) type | PCIE_ATU_FUNC_NUM(func_no));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PCIE_ATU_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Make sure ATU enable takes effect before any subsequent config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * and I/O accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) val = dw_pcie_readl_ob_unroll(pci, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PCIE_ATU_UNR_REGION_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (val & PCIE_ATU_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mdelay(LINK_WAIT_IATU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dev_err(pci->dev, "Outbound iATU is not being enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int index, int type, u64 cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u64 pci_addr, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 retries, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (pci->ops->cpu_addr_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (pci->iatu_unroll_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dw_pcie_prog_outbound_atu_unroll(pci, func_no, index, type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) cpu_addr, pci_addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PCIE_ATU_REGION_OUTBOUND | index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) lower_32_bits(cpu_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) upper_32_bits(cpu_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) lower_32_bits(cpu_addr + size - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) lower_32_bits(pci_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) upper_32_bits(pci_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PCIE_ATU_FUNC_NUM(func_no));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Make sure ATU enable takes effect before any subsequent config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * and I/O accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (val & PCIE_ATU_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mdelay(LINK_WAIT_IATU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(pci->dev, "Outbound iATU is not being enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u64 cpu_addr, u64 pci_addr, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __dw_pcie_prog_outbound_atu(pci, 0, index, type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cpu_addr, pci_addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void dw_pcie_prog_ep_outbound_atu(struct dw_pcie *pci, u8 func_no, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int type, u64 cpu_addr, u64 pci_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __dw_pcie_prog_outbound_atu(pci, func_no, index, type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cpu_addr, pci_addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static u32 dw_pcie_readl_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return dw_pcie_readl_atu(pci, offset + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void dw_pcie_writel_ib_unroll(struct dw_pcie *pci, u32 index, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 offset = PCIE_GET_ATU_INB_UNR_REG_OFFSET(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dw_pcie_writel_atu(pci, offset + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int index, int bar, u64 cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) enum dw_pcie_as_type as_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 retries, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) lower_32_bits(cpu_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) upper_32_bits(cpu_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) switch (as_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case DW_PCIE_AS_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) type = PCIE_ATU_TYPE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case DW_PCIE_AS_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) type = PCIE_ATU_TYPE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1, type |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PCIE_ATU_FUNC_NUM(func_no));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PCIE_ATU_FUNC_NUM_MATCH_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PCIE_ATU_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Make sure ATU enable takes effect before any subsequent config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * and I/O accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) val = dw_pcie_readl_ib_unroll(pci, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PCIE_ATU_UNR_REGION_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (val & PCIE_ATU_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) mdelay(LINK_WAIT_IATU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_err(pci->dev, "Inbound iATU is not being enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int bar, u64 cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) enum dw_pcie_as_type as_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 retries, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (pci->iatu_unroll_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return dw_pcie_prog_inbound_atu_unroll(pci, func_no, index, bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) cpu_addr, as_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_INBOUND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, lower_32_bits(cpu_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, upper_32_bits(cpu_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) switch (as_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case DW_PCIE_AS_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) type = PCIE_ATU_TYPE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case DW_PCIE_AS_IO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) type = PCIE_ATU_TYPE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PCIE_ATU_FUNC_NUM(func_no));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PCIE_ATU_FUNC_NUM_MATCH_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PCIE_ATU_BAR_MODE_ENABLE | (bar << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * Make sure ATU enable takes effect before any subsequent config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * and I/O accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (val & PCIE_ATU_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mdelay(LINK_WAIT_IATU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_err(pci->dev, "Inbound iATU is not being enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) enum dw_pcie_region_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case DW_PCIE_REGION_INBOUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) region = PCIE_ATU_REGION_INBOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case DW_PCIE_REGION_OUTBOUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) region = PCIE_ATU_REGION_OUTBOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int dw_pcie_wait_for_link(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Check if the link is up or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (dw_pcie_link_up(pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev_info(pci->dev, "Link up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_info(pci->dev, "Phy link never came up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int dw_pcie_link_up(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (pci->ops->link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return pci->ops->link_up(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) (!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) EXPORT_SYMBOL_GPL(dw_pcie_link_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) void dw_pcie_upconfig_setup(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) val = dw_pcie_readl_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) val |= PORT_MLTI_UPCFG_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dw_pcie_writel_dbi(pci, PCIE_PORT_MULTI_LANE_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 cap, ctrl2, link_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) switch (pcie_link_speed[link_gen]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case PCIE_SPEED_2_5GT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case PCIE_SPEED_5_0GT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) case PCIE_SPEED_8_0GT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case PCIE_SPEED_16_0GT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Use hardware capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ctrl2 &= ~PCI_EXP_LNKCTL2_HASD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (val == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) void dw_pcie_setup(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (pci->version >= 0x480A || (!pci->version &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dw_pcie_iatu_unroll_enabled(pci))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pci->iatu_unroll_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!pci->atu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pci->atu_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) devm_platform_ioremap_resource_byname(pdev, "atu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (IS_ERR(pci->atu_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (pci->link_gen > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dw_pcie_link_set_max_speed(pci, pci->link_gen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* Configure Gen1 N_FTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (pci->n_fts[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) val |= PORT_AFR_N_FTS(pci->n_fts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Configure Gen2+ N_FTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (pci->n_fts[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) val &= ~PORT_LOGIC_N_FTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) val |= pci->n_fts[pci->link_gen - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) val &= ~PORT_LINK_FAST_LINK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) val |= PORT_LINK_DLL_LINK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) of_property_read_u32(np, "num-lanes", &pci->num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!pci->num_lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_dbg(pci->dev, "Using h/w default number of lanes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Set the number of lanes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) val &= ~PORT_LINK_FAST_LINK_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) val &= ~PORT_LINK_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) switch (pci->num_lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) val |= PORT_LINK_MODE_1_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) val |= PORT_LINK_MODE_2_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) val |= PORT_LINK_MODE_4_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) val |= PORT_LINK_MODE_8_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Set link width speed control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) switch (pci->num_lanes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (of_property_read_bool(np, "snps,enable-cdm-check")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PCIE_PL_CHK_REG_CHK_REG_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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