^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe RC driver for Synopsys DesignWare Core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Joao Pinto <Joao.Pinto@synopsys.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct dw_plat_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) enum dw_pcie_device_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct dw_plat_pcie_of_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum dw_pcie_device_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct of_device_id dw_plat_pcie_of_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int dw_plat_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) dw_pcie_setup_rc(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) dw_pcie_wait_for_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) dw_pcie_msi_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void dw_plat_set_num_vectors(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pp->num_vectors = MAX_MSI_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .host_init = dw_plat_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .set_num_vectors = dw_plat_set_num_vectors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const struct dw_pcie_ops dw_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .start_link = dw_plat_pcie_establish_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum pci_barno bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dw_pcie_ep_reset_bar(pci, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) enum pci_epc_irq_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 interrupt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case PCI_EPC_IRQ_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return dw_pcie_ep_raise_legacy_irq(ep, func_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case PCI_EPC_IRQ_MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case PCI_EPC_IRQ_MSIX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_err(pci->dev, "UNKNOWN IRQ type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct pci_epc_features dw_plat_pcie_epc_features = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .linkup_notifier = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .msi_capable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .msix_capable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct pci_epc_features*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dw_plat_pcie_get_features(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return &dw_plat_pcie_epc_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct dw_pcie_ep_ops pcie_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .ep_init = dw_plat_pcie_ep_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .raise_irq = dw_plat_pcie_ep_raise_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .get_features = dw_plat_pcie_get_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct dw_pcie *pci = dw_plat_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pp->irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (pp->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return pp->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (IS_ENABLED(CONFIG_PCI_MSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pp->msi_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (pp->msi_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return pp->msi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pp->ops = &dw_plat_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ret = dw_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) dev_err(dev, "Failed to initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct dw_pcie_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct dw_pcie *pci = dw_plat_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ep = &pci->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ep->ops = &pcie_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (IS_ERR(pci->dbi_base2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return PTR_ERR(pci->dbi_base2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ep->phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ep->addr_size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ret = dw_pcie_ep_init(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(dev, "Failed to initialize endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int dw_plat_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct dw_plat_pcie *dw_plat_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct resource *res; /* Resource from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) const struct dw_plat_pcie_of_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) enum dw_pcie_device_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) match = of_match_device(dw_plat_pcie_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) data = (struct dw_plat_pcie_of_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mode = (enum dw_pcie_device_mode)data->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!dw_plat_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pci->ops = &dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dw_plat_pcie->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dw_plat_pcie->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pci->dbi_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (IS_ERR(pci->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) platform_set_drvdata(pdev, dw_plat_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) switch (dw_plat_pcie->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case DW_PCIE_RC_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_HOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case DW_PCIE_EP_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ret = dw_plat_add_pcie_ep(dw_plat_pcie, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .mode = DW_PCIE_RC_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const struct dw_plat_pcie_of_data dw_plat_pcie_ep_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .mode = DW_PCIE_EP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct of_device_id dw_plat_pcie_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .compatible = "snps,dw-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .data = &dw_plat_pcie_rc_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .compatible = "snps,dw-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .data = &dw_plat_pcie_ep_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct platform_driver dw_plat_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .name = "dw-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .of_match_table = dw_plat_pcie_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .probe = dw_plat_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) builtin_platform_driver(dw_plat_pcie_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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