^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe host controller driver for Axis ARTPEC-6 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Niklas Cassel <niklas.cassel@axis.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on work done by Phil Edworthy <phil@edworthys.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) enum artpec_pcie_variants {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ARTPEC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ARTPEC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct artpec6_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct regmap *regmap; /* DT axis,syscon-pcie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *phy_base; /* DT phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum artpec_pcie_variants variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum dw_pcie_device_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct artpec_pcie_of_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum artpec_pcie_variants variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum dw_pcie_device_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct of_device_id artpec6_pcie_of_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* ARTPEC-6 specific registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCIECFG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCIECFG_DBG_OEN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCIECFG_CORE_RESET_REQ BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCIECFG_LTSSM_ENABLE BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCIECFG_DEVICE_TYPE_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCIECFG_CLKREQ_B BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCIECFG_REFCLK_ENABLE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCIECFG_PLL_ENABLE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCIECFG_PCLK_ENABLE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCIECFG_RISRCREN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCIECFG_MODE_TX_DRV_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCIECFG_CISRREN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCIECFG_MACRO_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* ARTPEC-7 specific fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCIECFG_REFCLKSEL BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCIECFG_NOC_RESET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCIESTAT 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* ARTPEC-7 specific fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCIESTAT_EXTREFCLK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define NOCCFG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define NOCCFG_ENABLE_CLK_PCIE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define NOCCFG_POWER_PCIE_IDLEACK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NOCCFG_POWER_PCIE_IDLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define NOCCFG_POWER_PCIE_IDLEREQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PHY_STATUS 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PHY_COSPLLLOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PHY_TX_ASIC_OUT 0x4040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PHY_TX_ASIC_OUT_TX_ACK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PHY_RX_ASIC_OUT 0x405c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PHY_RX_ASIC_OUT_ACK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) regmap_read(artpec6_pcie->regmap, offset, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) regmap_write(artpec6_pcie->regmap, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct dw_pcie_ep *ep = &pci->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) switch (artpec6_pcie->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case DW_PCIE_RC_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return pci_addr - pp->cfg0_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case DW_PCIE_EP_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return pci_addr - ep->phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) dev_err(pci->dev, "UNKNOWN device type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int artpec6_pcie_establish_link(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) val |= PCIECFG_LTSSM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void artpec6_pcie_stop_link(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) val &= ~PCIECFG_LTSSM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct dw_pcie_ops dw_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .start_link = artpec6_pcie_establish_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .stop_link = artpec6_pcie_stop_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void artpec6_pcie_wait_for_phy_a6(struct artpec6_pcie *artpec6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct dw_pcie *pci = artpec6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) retries = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) retries--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) } while (retries &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev_err(dev, "PCIe clock manager did not leave idle state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) retries = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) val = readl(artpec6_pcie->phy_base + PHY_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) retries--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) } while (retries && !(val & PHY_COSPLLLOCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_err(dev, "PHY PLL did not lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void artpec6_pcie_wait_for_phy_a7(struct artpec6_pcie *artpec6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct dw_pcie *pci = artpec6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u16 phy_status_tx, phy_status_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) retries = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) retries--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } while (retries &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (!retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_err(dev, "PCIe clock manager did not leave idle state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) retries = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) phy_status_tx = readw(artpec6_pcie->phy_base + PHY_TX_ASIC_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) phy_status_rx = readw(artpec6_pcie->phy_base + PHY_RX_ASIC_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) retries--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } while (retries && ((phy_status_tx & PHY_TX_ASIC_OUT_TX_ACK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) (phy_status_rx & PHY_RX_ASIC_OUT_ACK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!retries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(dev, "PHY did not enter Pn state\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void artpec6_pcie_wait_for_phy(struct artpec6_pcie *artpec6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) switch (artpec6_pcie->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case ARTPEC6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) artpec6_pcie_wait_for_phy_a6(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) case ARTPEC7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) artpec6_pcie_wait_for_phy_a7(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void artpec6_pcie_init_phy_a6(struct artpec6_pcie *artpec6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PCIECFG_MODE_TX_DRV_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PCIECFG_CISRREN | /* Reference clock term. 100 Ohm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PCIECFG_MACRO_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) val |= PCIECFG_REFCLK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) val &= ~PCIECFG_DBG_OEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) val &= ~PCIECFG_CLKREQ_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) usleep_range(5000, 6000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) val |= NOCCFG_ENABLE_CLK_PCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) usleep_range(20, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) usleep_range(6000, 7000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void artpec6_pcie_init_phy_a7(struct artpec6_pcie *artpec6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct dw_pcie *pci = artpec6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) bool extrefclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Check if external reference clock is connected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val = artpec6_pcie_readl(artpec6_pcie, PCIESTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) extrefclk = !!(val & PCIESTAT_EXTREFCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_dbg(pci->dev, "Using reference clock: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) extrefclk ? "external" : "internal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PCIECFG_PCLK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (extrefclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) val |= PCIECFG_REFCLKSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val &= ~PCIECFG_REFCLKSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) val |= NOCCFG_ENABLE_CLK_PCIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) usleep_range(20, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void artpec6_pcie_init_phy(struct artpec6_pcie *artpec6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) switch (artpec6_pcie->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case ARTPEC6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) artpec6_pcie_init_phy_a6(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case ARTPEC7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) artpec6_pcie_init_phy_a7(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) switch (artpec6_pcie->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case ARTPEC6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val |= PCIECFG_CORE_RESET_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case ARTPEC7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) val &= ~PCIECFG_NOC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) switch (artpec6_pcie->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case ARTPEC6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) val &= ~PCIECFG_CORE_RESET_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case ARTPEC7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) val |= PCIECFG_NOC_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int artpec6_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (artpec6_pcie->variant == ARTPEC7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) pci->n_fts[0] = 180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pci->n_fts[1] = 180;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) artpec6_pcie_assert_core_reset(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) artpec6_pcie_init_phy(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) artpec6_pcie_deassert_core_reset(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) artpec6_pcie_wait_for_phy(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dw_pcie_setup_rc(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) artpec6_pcie_establish_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dw_pcie_wait_for_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dw_pcie_msi_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct dw_pcie_host_ops artpec6_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .host_init = artpec6_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct dw_pcie *pci = artpec6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (IS_ENABLED(CONFIG_PCI_MSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pp->msi_irq = platform_get_irq_byname(pdev, "msi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (pp->msi_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return pp->msi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pp->ops = &artpec6_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret = dw_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_err(dev, "failed to initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) enum pci_barno bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) artpec6_pcie_assert_core_reset(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) artpec6_pcie_init_phy(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) artpec6_pcie_deassert_core_reset(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) artpec6_pcie_wait_for_phy(artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dw_pcie_ep_reset_bar(pci, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) enum pci_epc_irq_type type, u16 interrupt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case PCI_EPC_IRQ_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case PCI_EPC_IRQ_MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(pci->dev, "UNKNOWN IRQ type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct dw_pcie_ep_ops pcie_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .ep_init = artpec6_pcie_ep_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .raise_irq = artpec6_pcie_raise_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int artpec6_add_pcie_ep(struct artpec6_pcie *artpec6_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct dw_pcie_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct dw_pcie *pci = artpec6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ep = &pci->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ep->ops = &pcie_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) pci->dbi_base2 = devm_platform_ioremap_resource_byname(pdev, "dbi2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (IS_ERR(pci->dbi_base2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return PTR_ERR(pci->dbi_base2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ep->phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ep->addr_size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ret = dw_pcie_ep_init(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_err(dev, "failed to initialize endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int artpec6_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct artpec6_pcie *artpec6_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) const struct artpec_pcie_of_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) enum artpec_pcie_variants variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) enum dw_pcie_device_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) match = of_match_device(artpec6_pcie_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) data = (struct artpec_pcie_of_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) variant = (enum artpec_pcie_variants)data->variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mode = (enum dw_pcie_device_mode)data->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!artpec6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pci->ops = &dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) artpec6_pcie->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) artpec6_pcie->variant = variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) artpec6_pcie->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (IS_ERR(pci->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) artpec6_pcie->phy_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) devm_platform_ioremap_resource_byname(pdev, "phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (IS_ERR(artpec6_pcie->phy_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return PTR_ERR(artpec6_pcie->phy_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) artpec6_pcie->regmap =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) "axis,syscon-pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (IS_ERR(artpec6_pcie->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return PTR_ERR(artpec6_pcie->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) platform_set_drvdata(pdev, artpec6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) switch (artpec6_pcie->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case DW_PCIE_RC_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_HOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case DW_PCIE_EP_TYPE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_EP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) val &= ~PCIECFG_DEVICE_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = artpec6_add_pcie_ep(artpec6_pcie, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dev_err(dev, "INVALID device type %d\n", artpec6_pcie->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const struct artpec_pcie_of_data artpec6_pcie_rc_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .variant = ARTPEC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .mode = DW_PCIE_RC_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const struct artpec_pcie_of_data artpec6_pcie_ep_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .variant = ARTPEC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .mode = DW_PCIE_EP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const struct artpec_pcie_of_data artpec7_pcie_rc_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .variant = ARTPEC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .mode = DW_PCIE_RC_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct artpec_pcie_of_data artpec7_pcie_ep_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .variant = ARTPEC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .mode = DW_PCIE_EP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct of_device_id artpec6_pcie_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .compatible = "axis,artpec6-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .data = &artpec6_pcie_rc_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .compatible = "axis,artpec6-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .data = &artpec6_pcie_ep_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .compatible = "axis,artpec7-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .data = &artpec7_pcie_rc_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .compatible = "axis,artpec7-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .data = &artpec7_pcie_ep_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static struct platform_driver artpec6_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .probe = artpec6_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .name = "artpec6-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .of_match_table = artpec6_pcie_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) builtin_platform_driver(artpec6_pcie_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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