^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe host controller driver for Amazon's Annapurna Labs IP (used in chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * such as Graviton and Alpine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Jonathan Chocron <jonnyc@amazon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci-ecam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci-acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "../../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct al_pcie_acpi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) void __iomem *dbi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static void __iomem *al_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct pci_config_window *cfg = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct al_pcie_acpi *pcie = cfg->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void __iomem *dbi_base = pcie->dbi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (bus->number == cfg->busr.start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * The DW PCIe core doesn't filter out transactions to other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * devices/functions on the root bus num, so we do this here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (PCI_SLOT(devfn) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return dbi_base + where;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return pci_ecam_map_bus(bus, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int al_pcie_init(struct pci_config_window *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct device *dev = cfg->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct acpi_device *adev = to_acpi_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct acpi_pci_root *root = acpi_driver_data(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct al_pcie_acpi *al_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (!al_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ret = acpi_get_rc_resources(dev, "AMZN0001", root->segment, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dev_err(dev, "can't get rc dbi base address for SEG %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) root->segment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev_dbg(dev, "Root port dbi res: %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) al_pcie->dbi_base = devm_pci_remap_cfg_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (IS_ERR(al_pcie->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return PTR_ERR(al_pcie->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cfg->priv = al_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct pci_ecam_ops al_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .bus_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .init = al_pcie_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .map_bus = al_pcie_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .read = pci_generic_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .write = pci_generic_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef CONFIG_PCIE_AL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AL_PCIE_REV_ID_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define AL_PCIE_REV_ID_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AL_PCIE_REV_ID_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AXI_BASE_OFFSET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DEVICE_ID_OFFSET 0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DEVICE_REV_ID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DEVICE_REV_ID_DEV_ID_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DEVICE_REV_ID_DEV_ID_X4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DEVICE_REV_ID_DEV_ID_X8 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DEVICE_REV_ID_DEV_ID_X16 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OB_CTRL_REV1_2_OFFSET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OB_CTRL_REV3_5_OFFSET 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CFG_TARGET_BUS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CFG_TARGET_BUS_MASK_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CFG_TARGET_BUS_BUSNUM_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CFG_CONTROL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CFG_CONTROL_SUBBUS_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CFG_CONTROL_SEC_BUS_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct al_pcie_reg_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int ob_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct al_pcie_target_bus_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 ecam_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct al_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void __iomem *controller_base; /* base of PCIe unit (not DW core) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) resource_size_t ecam_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int controller_rev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct al_pcie_reg_offsets reg_offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct al_pcie_target_bus_cfg target_bus_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PCIE_ECAM_DEVFN(x) (((x) & 0xff) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define to_al_pcie(x) dev_get_drvdata((x)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline u32 al_pcie_controller_readl(struct al_pcie *pcie, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return readl_relaxed(pcie->controller_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline void al_pcie_controller_writel(struct al_pcie *pcie, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel_relaxed(val, pcie->controller_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int *rev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 dev_rev_id_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 dev_id_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_rev_id_val = al_pcie_controller_readl(pcie, AXI_BASE_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DEVICE_ID_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEVICE_REV_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_id_val = FIELD_GET(DEVICE_REV_ID_DEV_ID_MASK, dev_rev_id_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) switch (dev_id_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case DEVICE_REV_ID_DEV_ID_X4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *rev_id = AL_PCIE_REV_ID_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case DEVICE_REV_ID_DEV_ID_X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *rev_id = AL_PCIE_REV_ID_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case DEVICE_REV_ID_DEV_ID_X16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *rev_id = AL_PCIE_REV_ID_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(pcie->dev, "Unsupported dev_id_val (0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dev_id_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_dbg(pcie->dev, "dev_id_val: 0x%x\n", dev_id_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int al_pcie_reg_offsets_set(struct al_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) switch (pcie->controller_rev_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case AL_PCIE_REV_ID_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case AL_PCIE_REV_ID_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case AL_PCIE_REV_ID_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(pcie->dev, "Unsupported controller rev_id: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pcie->controller_rev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 target_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u8 mask_target_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) reg = FIELD_PREP(CFG_TARGET_BUS_MASK_MASK, mask_target_bus) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) FIELD_PREP(CFG_TARGET_BUS_BUSNUM_MASK, target_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) al_pcie_controller_writel(pcie, AXI_BASE_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pcie->reg_offsets.ob_ctrl + CFG_TARGET_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int devfn, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct pcie_port *pp = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct al_pcie *pcie = to_al_pcie(to_dw_pcie_from_pp(pp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int busnr = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) void __iomem *pci_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) (busnr_ecam << 20) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PCIE_ECAM_DEVFN(devfn));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (busnr_reg != target_bus_cfg->reg_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) target_bus_cfg->reg_val, busnr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) target_bus_cfg->reg_val = busnr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) al_pcie_target_bus_set(pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) target_bus_cfg->reg_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) target_bus_cfg->reg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return pci_base_addr + where;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct pci_ops al_child_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .map_bus = al_pcie_conf_addr_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .read = pci_generic_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .write = pci_generic_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void al_pcie_config_prepare(struct al_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct al_pcie_target_bus_cfg *target_bus_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct pcie_port *pp = &pcie->pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int ecam_bus_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 cfg_control_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 subordinate_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u8 secondary_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 cfg_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct resource *bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) target_bus_cfg = &pcie->target_bus_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ecam_bus_mask = (pcie->ecam_size >> 20) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (ecam_bus_mask > 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ecam_bus_mask = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* This portion is taken from the transaction address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) target_bus_cfg->ecam_mask = ecam_bus_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* This portion is taken from the cfg_target_bus reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) target_bus_cfg->reg_val = bus->start & target_bus_cfg->reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) target_bus_cfg->reg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) secondary_bus = bus->start + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) subordinate_bus = bus->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Set the valid values of secondary and subordinate buses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CFG_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cfg_control = al_pcie_controller_readl(pcie, cfg_control_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) reg = cfg_control &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ~(CFG_CONTROL_SEC_BUS_MASK | CFG_CONTROL_SUBBUS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) reg |= FIELD_PREP(CFG_CONTROL_SUBBUS_MASK, subordinate_bus) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) FIELD_PREP(CFG_CONTROL_SEC_BUS_MASK, secondary_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) al_pcie_controller_writel(pcie, cfg_control_offset, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int al_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct al_pcie *pcie = to_al_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pp->bridge->child_ops = &al_child_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) rc = al_pcie_reg_offsets_set(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) al_pcie_config_prepare(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct dw_pcie_host_ops al_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .host_init = al_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int al_add_pcie_port(struct pcie_port *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pp->ops = &al_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = dw_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_err(dev, "failed to initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct dw_pcie_ops dw_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int al_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct resource *controller_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct resource *ecam_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct resource *dbi_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct al_pcie *al_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!al_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pci->ops = &dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) al_pcie->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) al_pcie->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (IS_ERR(pci->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ecam_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (!ecam_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_err(dev, "couldn't find 'config' reg in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) al_pcie->ecam_size = resource_size(ecam_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) controller_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) al_pcie->controller_base = devm_ioremap_resource(dev, controller_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (IS_ERR(al_pcie->controller_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_err(dev, "couldn't remap controller base %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) controller_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return PTR_ERR(al_pcie->controller_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_dbg(dev, "From DT: dbi_base: %pR, controller_base: %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dbi_res, controller_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) platform_set_drvdata(pdev, al_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return al_add_pcie_port(&pci->pp, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const struct of_device_id al_pcie_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { .compatible = "amazon,al-alpine-v2-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { .compatible = "amazon,al-alpine-v3-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct platform_driver al_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .name = "al-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .of_match_table = al_pcie_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .probe = al_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) builtin_platform_driver(al_pcie_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #endif /* CONFIG_PCIE_AL*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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