Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PCIe host controller driver for Amlogic MESON SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2018 Amlogic, inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Yue Wang <yue.wang@amlogic.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define to_meson_pcie(x) dev_get_drvdata((x)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PCIE_CAP_MAX_PAYLOAD_SIZE(x)	((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PCIE_CAP_MAX_READ_REQ_SIZE(x)	((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* PCIe specific config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PCIE_CFG0			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define APP_LTSSM_ENABLE		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define PCIE_CFG_STATUS12		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IS_SMLH_LINK_UP(x)		((x) & (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define IS_RDLH_LINK_UP(x)		((x) & (1 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IS_LTSSM_UP(x)			((((x) >> 10) & 0x1f) == 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define PCIE_CFG_STATUS17		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PM_CURRENT_STATE(x)		(((x) >> 7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WAIT_LINKUP_TIMEOUT		4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PORT_CLK_RATE			100000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MAX_PAYLOAD_SIZE		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MAX_READ_REQ_SIZE		256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PCIE_RESET_DELAY		500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PCIE_SHARED_RESET		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PCIE_NORMAL_RESET		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) enum pcie_data_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	PCIE_GEN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	PCIE_GEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	PCIE_GEN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	PCIE_GEN4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) struct meson_pcie_clk_res {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct clk *port_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct clk *general_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct meson_pcie_rc_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct reset_control *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct reset_control *apb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct meson_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct dw_pcie pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	void __iomem *cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct meson_pcie_clk_res clk_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct meson_pcie_rc_reset mrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct phy *phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 						  const char *id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 						  u32 reset_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct device *dev = mp->pci.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (reset_type == PCIE_SHARED_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		reset = devm_reset_control_get_shared(dev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		reset = devm_reset_control_get(dev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static int meson_pcie_get_resets(struct meson_pcie *mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct meson_pcie_rc_reset *mrst = &mp->mrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (IS_ERR(mrst->port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return PTR_ERR(mrst->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	reset_control_deassert(mrst->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (IS_ERR(mrst->apb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return PTR_ERR(mrst->apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	reset_control_deassert(mrst->apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int meson_pcie_get_mems(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			       struct meson_pcie *mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct dw_pcie *pci = &mp->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (IS_ERR(pci->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	if (IS_ERR(mp->cfg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		return PTR_ERR(mp->cfg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int meson_pcie_power_on(struct meson_pcie *mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	ret = phy_init(mp->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	ret = phy_power_on(mp->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		phy_exit(mp->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void meson_pcie_power_off(struct meson_pcie *mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	phy_power_off(mp->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	phy_exit(mp->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int meson_pcie_reset(struct meson_pcie *mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct meson_pcie_rc_reset *mrst = &mp->mrst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ret = phy_reset(mp->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	reset_control_assert(mrst->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	reset_control_assert(mrst->apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	udelay(PCIE_RESET_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	reset_control_deassert(mrst->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	reset_control_deassert(mrst->apb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	udelay(PCIE_RESET_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static inline struct clk *meson_pcie_probe_clock(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 						 const char *id, u64 rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	clk = devm_clk_get(dev, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		ret = clk_set_rate(clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			dev_err(dev, "set clk rate failed, ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		dev_err(dev, "couldn't enable clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	devm_add_action_or_reset(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				 (void (*) (void *))clk_disable_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				 clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int meson_pcie_probe_clocks(struct meson_pcie *mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct device *dev = mp->pci.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct meson_pcie_clk_res *res = &mp->clk_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (IS_ERR(res->port_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return PTR_ERR(res->port_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (IS_ERR(res->general_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return PTR_ERR(res->general_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (IS_ERR(res->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return PTR_ERR(res->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return readl(mp->cfg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	writel(val, mp->cfg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void meson_pcie_assert_reset(struct meson_pcie *mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	gpiod_set_value_cansleep(mp->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	udelay(500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	gpiod_set_value_cansleep(mp->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void meson_pcie_init_dw(struct meson_pcie *mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	val = meson_cfg_readl(mp, PCIE_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	val |= APP_LTSSM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	meson_cfg_writel(mp, val, PCIE_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int meson_size_to_payload(struct meson_pcie *mp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct device *dev = mp->pci.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 * So if input size is not 2^order alignment or less than 2^7 or bigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 * than 2^12, just set to default size 2^(1+7).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (!is_power_of_2(size) || size < 128 || size > 4096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		dev_warn(dev, "payload size %d, set to default 256\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	return fls(size) - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void meson_set_max_payload(struct meson_pcie *mp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct dw_pcie *pci = &mp->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int max_payload_size = meson_size_to_payload(mp, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	val &= ~PCI_EXP_DEVCTL_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct dw_pcie *pci = &mp->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	int max_rd_req_size = meson_size_to_payload(mp, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	val &= ~PCI_EXP_DEVCTL_READRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int meson_pcie_establish_link(struct meson_pcie *mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct dw_pcie *pci = &mp->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	meson_pcie_init_dw(mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	dw_pcie_setup_rc(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	meson_pcie_assert_reset(mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	return dw_pcie_wait_for_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 				  int where, int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	ret = pci_generic_config_read(bus, devfn, where, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (ret != PCIBIOS_SUCCESSFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	 * There is a bug in the MESON AXG PCIe controller whereby software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	 * the return value in the config accessors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (where == PCI_CLASS_REVISION && size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		*val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	else if (where == PCI_CLASS_DEVICE && size == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		*val = PCI_CLASS_BRIDGE_PCI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	else if (where == PCI_CLASS_DEVICE && size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		*val = PCI_CLASS_BRIDGE_PCI & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	else if (where == PCI_CLASS_DEVICE + 1 && size == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		*val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct pci_ops meson_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.map_bus = dw_pcie_own_conf_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.read = meson_pcie_rd_own_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.write = pci_generic_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int meson_pcie_link_up(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	struct meson_pcie *mp = to_meson_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	u32 speed_okay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	u32 cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		smlh_up = IS_SMLH_LINK_UP(state12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		rdlh_up = IS_RDLH_LINK_UP(state12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		ltssm_up = IS_LTSSM_UP(state12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 			speed_okay = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		if (smlh_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			dev_dbg(dev, "smlh_link_up is on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		if (rdlh_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			dev_dbg(dev, "rdlh_link_up is on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		if (ltssm_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			dev_dbg(dev, "ltssm_up is on\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		if (speed_okay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			dev_dbg(dev, "speed_okay\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		if (smlh_up && rdlh_up && ltssm_up && speed_okay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	} while (cnt < WAIT_LINKUP_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	dev_err(dev, "error: wait linkup timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int meson_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	struct meson_pcie *mp = to_meson_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	pp->bridge->ops = &meson_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	ret = meson_pcie_establish_link(mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	dw_pcie_msi_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct dw_pcie_host_ops meson_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.host_init = meson_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int meson_add_pcie_port(struct meson_pcie *mp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			       struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	struct dw_pcie *pci = &mp->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		pp->msi_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		if (pp->msi_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 			return pp->msi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	pp->ops = &meson_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	ret = dw_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		dev_err(dev, "failed to initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct dw_pcie_ops dw_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	.link_up = meson_pcie_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int meson_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	struct meson_pcie *mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	if (!mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	pci = &mp->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	pci->ops = &dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	pci->num_lanes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	mp->phy = devm_phy_get(dev, "pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	if (IS_ERR(mp->phy)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		return PTR_ERR(mp->phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	if (IS_ERR(mp->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		dev_err(dev, "get reset gpio failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		return PTR_ERR(mp->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	ret = meson_pcie_get_resets(mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		dev_err(dev, "get reset resource failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	ret = meson_pcie_get_mems(pdev, mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		dev_err(dev, "get memory resource failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	ret = meson_pcie_power_on(mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		dev_err(dev, "phy power on failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	ret = meson_pcie_reset(mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		dev_err(dev, "reset failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		goto err_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	ret = meson_pcie_probe_clocks(mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		dev_err(dev, "init clock resources failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		goto err_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	platform_set_drvdata(pdev, mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	ret = meson_add_pcie_port(mp, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		dev_err(dev, "Add PCIe port failed, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		goto err_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) err_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	meson_pcie_power_off(mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const struct of_device_id meson_pcie_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		.compatible = "amlogic,axg-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		.compatible = "amlogic,g12a-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODULE_DEVICE_TABLE(of, meson_pcie_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static struct platform_driver meson_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	.probe = meson_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		.name = "meson-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		.of_match_table = meson_pcie_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) module_platform_driver(meson_pcie_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MODULE_AUTHOR("Yue Wang <yue.wang@amlogic.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_DESCRIPTION("Amlogic PCIe Controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MODULE_LICENSE("GPL v2");