^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe host controller driver for Freescale Layerscape SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Freescale Semiconductor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* PEX1/2 Misc Ports Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LTSSM_STATE_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LTSSM_STATE_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LTSSM_PCIE_L0 0x11 /* L0 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* PEX Internal Configuration Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCIE_IATU_NUM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct ls_pcie_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 lut_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 ltssm_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 lut_dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const struct dw_pcie_host_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const struct dw_pcie_ops *dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct ls_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *lut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct regmap *scfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const struct ls_pcie_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define to_ls_pcie(x) dev_get_drvdata((x)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct dw_pcie *pci = pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 header_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) header_type &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return header_type == PCI_HEADER_TYPE_BRIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Clear multi-function bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct dw_pcie *pci = pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Drop MSG TLP except for Vendor MSG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct dw_pcie *pci = pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) val = ioread32(pci->dbi_base + PCIE_STRFMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val &= 0xDFFFFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) for (i = 0; i < PCIE_IATU_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dw_pcie_disable_atu(pcie->pci, i, DW_PCIE_REGION_OUTBOUND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int ls1021_pcie_link_up(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct ls_pcie *pcie = to_ls_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (!pcie->scfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (state < LTSSM_PCIE_L0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int ls_pcie_link_up(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct ls_pcie *pcie = to_ls_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pcie->drvdata->ltssm_shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) LTSSM_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (state < LTSSM_PCIE_L0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Forward error response of outbound non-posted requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct dw_pcie *pci = pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int ls_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct ls_pcie *pcie = to_ls_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Disable outbound windows configured by the bootloader to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * one transaction hitting multiple outbound windows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * dw_pcie_setup_rc() will reconfigure the outbound windows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ls_pcie_disable_outbound_atus(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ls_pcie_fix_error_response(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dw_pcie_dbi_ro_wr_en(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ls_pcie_clear_multifunction(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dw_pcie_dbi_ro_wr_dis(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ls_pcie_drop_msg_tlp(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dw_pcie_setup_rc(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int ls1021_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct ls_pcie *pcie = to_ls_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 index[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "fsl,pcie-scfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (IS_ERR(pcie->scfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = PTR_ERR(pcie->scfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_err(dev, "No syscfg phandle specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pcie->scfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (of_property_read_u32_array(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "fsl,pcie-scfg", index, 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pcie->scfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pcie->index = index[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ls_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int ls_pcie_msi_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct device_node *msi_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * The MSI domain is set by the generic of_msi_configure(). This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * .msi_host_init() function keeps us from doing the default MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * domain setup in dw_pcie_host_init() and also enforces the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * requirement that "msi-parent" exists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) msi_node = of_parse_phandle(np, "msi-parent", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!msi_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(dev, "failed to find msi-parent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) of_node_put(msi_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct dw_pcie_host_ops ls1021_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .host_init = ls1021_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .msi_host_init = ls_pcie_msi_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const struct dw_pcie_host_ops ls_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .host_init = ls_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .msi_host_init = ls_pcie_msi_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct dw_pcie_ops dw_ls1021_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .link_up = ls1021_pcie_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct dw_pcie_ops dw_ls_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .link_up = ls_pcie_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct ls_pcie_drvdata ls1021_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .ops = &ls1021_pcie_host_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .dw_pcie_ops = &dw_ls1021_pcie_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct ls_pcie_drvdata ls1043_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .lut_offset = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .ltssm_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .lut_dbg = 0x7fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .ops = &ls_pcie_host_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .dw_pcie_ops = &dw_ls_pcie_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct ls_pcie_drvdata ls1046_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .lut_offset = 0x80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .ltssm_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .lut_dbg = 0x407fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .ops = &ls_pcie_host_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .dw_pcie_ops = &dw_ls_pcie_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct ls_pcie_drvdata ls2080_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .lut_offset = 0x80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .ltssm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .lut_dbg = 0x7fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .ops = &ls_pcie_host_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .dw_pcie_ops = &dw_ls_pcie_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct ls_pcie_drvdata ls2088_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .lut_offset = 0x80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .ltssm_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .lut_dbg = 0x407fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .ops = &ls_pcie_host_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .dw_pcie_ops = &dw_ls_pcie_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct of_device_id ls_pcie_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { .compatible = "fsl,ls1028a-pcie", .data = &ls2088_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { .compatible = "fsl,ls1088a-pcie", .data = &ls2088_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int __init ls_add_pcie_port(struct ls_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct dw_pcie *pci = pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pp->ops = pcie->drvdata->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = dw_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_err(dev, "failed to initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int __init ls_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct ls_pcie *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct resource *dbi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pcie->drvdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pci->ops = pcie->drvdata->dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pcie->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (IS_ERR(pci->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!ls_pcie_is_bridge(pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) platform_set_drvdata(pdev, pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = ls_add_pcie_port(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct platform_driver ls_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .name = "layerscape-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .of_match_table = ls_pcie_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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