^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe controller EP driver for Freescale Layerscape SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 NXP Semiconductor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct ls_pcie_ep_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 func_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) const struct dw_pcie_ep_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) const struct dw_pcie_ops *dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct ls_pcie_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct pci_epc_features *ls_epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) const struct ls_pcie_ep_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int ls_pcie_establish_link(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct dw_pcie_ops dw_ls_pcie_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .start_link = ls_pcie_establish_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const struct pci_epc_features*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return pcie->ls_epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct dw_pcie_ep_func *ep_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum pci_barno bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!ep_func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dw_pcie_ep_reset_bar(pci, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum pci_epc_irq_type type, u16 interrupt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case PCI_EPC_IRQ_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return dw_pcie_ep_raise_legacy_irq(ep, func_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case PCI_EPC_IRQ_MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case PCI_EPC_IRQ_MSIX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev_err(pci->dev, "UNKNOWN IRQ type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 func_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) WARN_ON(func_no && !pcie->drvdata->func_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return pcie->drvdata->func_offset * func_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct dw_pcie_ep_ops ls_pcie_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .ep_init = ls_pcie_ep_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .raise_irq = ls_pcie_ep_raise_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .get_features = ls_pcie_ep_get_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .func_conf_select = ls_pcie_ep_func_conf_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .ops = &ls_pcie_ep_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .dw_pcie_ops = &dw_ls_pcie_ep_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct ls_pcie_ep_drvdata ls2_ep_drvdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .func_offset = 0x20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .ops = &ls_pcie_ep_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .dw_pcie_ops = &dw_ls_pcie_ep_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct of_device_id ls_pcie_ep_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { .compatible = "fsl,ls1046a-pcie-ep", .data = &ls1_ep_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { .compatible = "fsl,ls1088a-pcie-ep", .data = &ls2_ep_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { .compatible = "fsl,ls2088a-pcie-ep", .data = &ls2_ep_drvdata },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct dw_pcie *pci = pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct dw_pcie_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ep = &pci->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ep->ops = pcie->drvdata->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ep->phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ep->addr_size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = dw_pcie_ep_init(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_err(dev, "failed to initialize endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int __init ls_pcie_ep_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct ls_pcie_ep *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct pci_epc_features *ls_epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct resource *dbi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ls_epc = devm_kzalloc(dev, sizeof(*ls_epc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!ls_epc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pcie->drvdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pci->ops = pcie->drvdata->dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ls_epc->bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pcie->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) pcie->ls_epc = ls_epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (IS_ERR(pci->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) platform_set_drvdata(pdev, pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = ls_add_pcie_ep(pcie, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct platform_driver ls_pcie_ep_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "layerscape-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .of_match_table = ls_pcie_ep_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags