^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCIe host controller driver for Freescale i.MX6 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Kosagi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * https://www.kosagi.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Sean Cross <xobs@kosagi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum imx6_pcie_variants {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) IMX6Q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) IMX6SX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) IMX6QP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) IMX7D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) IMX8MQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct imx6_pcie_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum imx6_pcie_variants variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int dbi_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct imx6_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) bool gpio_active_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct clk *pcie_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk *pcie_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct clk *pcie_inbound_axi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct clk *pcie_aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct regmap *iomuxc_gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 controller_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct reset_control *pciephy_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct reset_control *apps_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct reset_control *turnoff_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 tx_deemph_gen1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 tx_deemph_gen2_3p5db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 tx_deemph_gen2_6db;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 tx_swing_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 tx_swing_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct regulator *vpcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *phy_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* power domain for pcie */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct device *pd_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* power domain for pcie phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct device *pd_pcie_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct imx6_pcie_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* PCIe Port Logic registers (memory-mapped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PL_OFFSET 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCIE_PHY_CTRL_CAP_ADR BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCIE_PHY_CTRL_CAP_DAT BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCIE_PHY_CTRL_WR BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCIE_PHY_CTRL_RD BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCIE_PHY_STAT_ACK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* PHY registers (not memory-mapped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCIE_PHY_ATEOVRD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCIE_PHY_ATEOVRD_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCIE_PHY_RX_ASIC_OUT 0x100D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* iMX7 PCIe PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCIE_PHY_CMN_REG4 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* These are probably the bits that *aren't* DCC_FB_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCIE_PHY_CMN_REG4_DCC_FB_EN 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCIE_PHY_CMN_REG15 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCIE_PHY_CMN_REG15_DLY_4 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PCIE_PHY_CMN_REG15_PLL_PD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PCIE_PHY_CMN_REG15_OVRD_PLL_PD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PCIE_PHY_CMN_REG24 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PCIE_PHY_CMN_REG24_RX_EQ BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PCIE_PHY_CMN_REG26 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PHY_RX_OVRD_IN_LO 0x1005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct dw_pcie *pci = imx6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 max_iterations = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 wait_counter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PCIE_PHY_STAT_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) wait_counter++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (val == exp_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } while (wait_counter < max_iterations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct dw_pcie *pci = imx6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) val = PCIE_PHY_CTRL_DATA(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) val |= PCIE_PHY_CTRL_CAP_ADR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = pcie_phy_poll_ack(imx6_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) val = PCIE_PHY_CTRL_DATA(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return pcie_phy_poll_ack(imx6_pcie, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct dw_pcie *pci = imx6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 phy_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = pcie_phy_wait_ack(imx6_pcie, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* assert Read signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) phy_ctl = PCIE_PHY_CTRL_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = pcie_phy_poll_ack(imx6_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* deassert Read signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return pcie_phy_poll_ack(imx6_pcie, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct dw_pcie *pci = imx6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* write addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* cap addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = pcie_phy_wait_ack(imx6_pcie, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) var = PCIE_PHY_CTRL_DATA(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* capture data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) var |= PCIE_PHY_CTRL_CAP_DAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = pcie_phy_poll_ack(imx6_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* deassert cap data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) var = PCIE_PHY_CTRL_DATA(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* wait for ack de-assertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = pcie_phy_poll_ack(imx6_pcie, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* assert wr signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) var = PCIE_PHY_CTRL_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* wait for ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = pcie_phy_poll_ack(imx6_pcie, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* deassert wr signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) var = PCIE_PHY_CTRL_DATA(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* wait for ack de-assertion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = pcie_phy_poll_ack(imx6_pcie, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PHY_RX_OVRD_IN_LO_RX_PLL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) usleep_range(2000, 3000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PHY_RX_OVRD_IN_LO_RX_PLL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Added for PCI abort handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int imx6q_pcie_abort_handler(unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int fsr, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned long pc = instruction_pointer(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned long instr = *(unsigned long *)pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int reg = (instr >> 12) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * If the instruction being executed was a read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * make it look like it read all-ones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if ((instr & 0x0c100000) == 0x04100000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (instr & 0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) val = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) regs->uregs[reg] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regs->ARM_pc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if ((instr & 0x0e100090) == 0x00100090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) regs->uregs[reg] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) regs->ARM_pc += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int imx6_pcie_attach_pd(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct device_link *link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Do nothing when in a single power domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (dev->pm_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (IS_ERR(imx6_pcie->pd_pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return PTR_ERR(imx6_pcie->pd_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Do nothing when power domain missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!imx6_pcie->pd_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) link = device_link_add(dev, imx6_pcie->pd_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DL_FLAG_STATELESS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) DL_FLAG_PM_RUNTIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) DL_FLAG_RPM_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(dev, "Failed to add device_link to pcie pd.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (IS_ERR(imx6_pcie->pd_pcie_phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return PTR_ERR(imx6_pcie->pd_pcie_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DL_FLAG_STATELESS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DL_FLAG_PM_RUNTIME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DL_FLAG_RPM_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(dev, "Failed to add device_link to pcie_phy pd.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct device *dev = imx6_pcie->pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) switch (imx6_pcie->drvdata->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case IMX7D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case IMX8MQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) reset_control_assert(imx6_pcie->pciephy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) reset_control_assert(imx6_pcie->apps_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case IMX6SX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Force PCIe PHY reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) IMX6SX_GPR5_PCIE_BTNRST_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) IMX6SX_GPR5_PCIE_BTNRST_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case IMX6QP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) IMX6Q_GPR1_PCIE_SW_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) IMX6Q_GPR1_PCIE_SW_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case IMX6Q:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int ret = regulator_disable(imx6_pcie->vpcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(dev, "failed to disable vpcie regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct dw_pcie *pci = imx6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) switch (imx6_pcie->drvdata->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case IMX6SX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_err(dev, "unable to enable pcie_axi clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case IMX6QP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case IMX6Q:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* power up core phy and enable ref clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * the async reset input need ref clock to sync internally,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * when the ref clock comes after reset, internal synced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * reset time is too short, cannot meet the requirement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * add one ~10us delay here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) usleep_range(10, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case IMX7D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case IMX8MQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = clk_prepare_enable(imx6_pcie->pcie_aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(dev, "unable to enable pcie_aux clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) offset = imx6_pcie_grp_offset(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Set the over ride low and enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * make sure that REF_CLK is turned on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct device *dev = imx6_pcie->pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) IOMUXC_GPR22, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PHY_PLL_LOCK_WAIT_USLEEP_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PHY_PLL_LOCK_WAIT_TIMEOUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(dev, "PCIe PLL lock timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct dw_pcie *pci = imx6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = regulator_enable(imx6_pcie->vpcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_err(dev, "failed to enable vpcie regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = clk_prepare_enable(imx6_pcie->pcie_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(dev, "unable to enable pcie_phy clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto err_pcie_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = clk_prepare_enable(imx6_pcie->pcie_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(dev, "unable to enable pcie_bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) goto err_pcie_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret = clk_prepare_enable(imx6_pcie->pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dev_err(dev, "unable to enable pcie clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) goto err_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = imx6_pcie_enable_ref_clk(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_err(dev, "unable to enable pcie ref clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) goto err_ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* allow the clocks to stabilize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) usleep_range(200, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Some boards don't have PCIe reset GPIO. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (gpio_is_valid(imx6_pcie->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) gpio_set_value_cansleep(imx6_pcie->reset_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) imx6_pcie->gpio_active_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) gpio_set_value_cansleep(imx6_pcie->reset_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) !imx6_pcie->gpio_active_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) switch (imx6_pcie->drvdata->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case IMX8MQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) reset_control_deassert(imx6_pcie->pciephy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case IMX7D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) reset_control_deassert(imx6_pcie->pciephy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Workaround for ERR010728, failure of PCI-e PLL VCO to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * oscillate, especially when cold. This turns off "Duty-cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * Corrector" and other mysterious undocumented things.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (likely(imx6_pcie->phy_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* De-assert DCC_FB_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Assert RX_EQS and RX_EQS_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) | PCIE_PHY_CMN_REG24_RX_EQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Assert ATT_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) writel(PCIE_PHY_CMN_REG26_ATT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case IMX6SX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case IMX6QP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) IMX6Q_GPR1_PCIE_SW_RST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) usleep_range(200, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case IMX6Q: /* Nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) err_ref_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) clk_disable_unprepare(imx6_pcie->pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) err_pcie:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) clk_disable_unprepare(imx6_pcie->pcie_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) err_pcie_bus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) clk_disable_unprepare(imx6_pcie->pcie_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) err_pcie_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = regulator_disable(imx6_pcie->vpcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(dev, "failed to disable vpcie regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (imx6_pcie->drvdata->variant == IMX8MQ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) imx6_pcie->controller_id == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PCI_EXP_TYPE_ROOT_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mask = IMX6Q_GPR12_DEVICE_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PCI_EXP_TYPE_ROOT_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) switch (imx6_pcie->drvdata->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case IMX8MQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * TODO: Currently this code assumes external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * oscillator is being used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) regmap_update_bits(imx6_pcie->iomuxc_gpr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) imx6_pcie_grp_offset(imx6_pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) IMX8MQ_GPR_PCIE_REF_USE_PAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) IMX8MQ_GPR_PCIE_REF_USE_PAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case IMX7D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) case IMX6SX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) IMX6SX_GPR12_PCIE_RX_EQ_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) IMX6SX_GPR12_PCIE_RX_EQ_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* configure constant input signal to the pcie ctrl and phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) IMX6Q_GPR8_TX_DEEMPH_GEN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) imx6_pcie->tx_deemph_gen1 << 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) imx6_pcie->tx_deemph_gen2_3p5db << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) imx6_pcie->tx_deemph_gen2_6db << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) IMX6Q_GPR8_TX_SWING_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) imx6_pcie->tx_swing_full << 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) IMX6Q_GPR8_TX_SWING_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) imx6_pcie->tx_swing_low << 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) imx6_pcie_configure_type(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) int mult, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) switch (phy_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) case 125000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * The default settings of the MPLL are for a 125MHz input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * clock, so no need to reconfigure anything in that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) case 100000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mult = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case 200000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) mult = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_err(imx6_pcie->pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "Unsupported PHY reference clock rate %lu\n", phy_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) val |= PCIE_PHY_ATEOVRD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct dw_pcie *pci = imx6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) for (retries = 0; retries < 200; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Test if the speed change finished. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) usleep_range(100, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev_err(dev, "Speed change timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static void imx6_pcie_ltssm_enable(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) switch (imx6_pcie->drvdata->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case IMX6Q:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case IMX6SX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case IMX6QP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) IMX6Q_GPR12_PCIE_CTL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) IMX6Q_GPR12_PCIE_CTL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case IMX7D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case IMX8MQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) reset_control_deassert(imx6_pcie->apps_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct dw_pcie *pci = imx6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * Force Gen1 operation when starting the link. In case the link is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * started in Gen2 mode, there is a possibility the devices on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * bus will not be detected at all. This happens with PCIe switches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) tmp &= ~PCI_EXP_LNKCAP_SLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* Start LTSSM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) imx6_pcie_ltssm_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ret = dw_pcie_wait_for_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) goto err_reset_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (pci->link_gen == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Allow Gen2 mode after the link is up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) tmp &= ~PCI_EXP_LNKCAP_SLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) tmp |= PCI_EXP_LNKCAP_SLS_5_0GB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * Start Directed Speed Change so the best possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * speed both link partners support can be negotiated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) tmp |= PORT_LOGIC_SPEED_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (imx6_pcie->drvdata->flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * from i.MX6 family when no link speed transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * occurs and we go Gen1 -> yep, Gen1. The difference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * is that, in such case, it will not be cleared by HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * which will cause the following code to report false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) dev_err(dev, "Failed to bring link up!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) goto err_reset_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* Make sure link training is finished as well! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = dw_pcie_wait_for_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_err(dev, "Failed to bring link up!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) goto err_reset_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev_info(dev, "Link: Gen2 disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) err_reset_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) imx6_pcie_reset_phy(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int imx6_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) imx6_pcie_assert_core_reset(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) imx6_pcie_init_phy(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) imx6_pcie_deassert_core_reset(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) imx6_setup_phy_mpll(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dw_pcie_setup_rc(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) imx6_pcie_establish_link(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dw_pcie_msi_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .host_init = imx6_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct dw_pcie *pci = imx6_pcie->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (IS_ENABLED(CONFIG_PCI_MSI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pp->msi_irq = platform_get_irq_byname(pdev, "msi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (pp->msi_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return pp->msi_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) pp->ops = &imx6_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret = dw_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_err(dev, "failed to initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const struct dw_pcie_ops dw_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /* No special ops needed, but pcie-designware still expects this struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static void imx6_pcie_ltssm_disable(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) switch (imx6_pcie->drvdata->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) case IMX6SX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case IMX6QP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) IMX6Q_GPR12_PCIE_CTL_2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case IMX7D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) reset_control_assert(imx6_pcie->apps_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_err(dev, "ltssm_disable not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct device *dev = imx6_pcie->pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Some variants have a turnoff reset in DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (imx6_pcie->turnoff_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) reset_control_assert(imx6_pcie->turnoff_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) reset_control_deassert(imx6_pcie->turnoff_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) goto pm_turnoff_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* Others poke directly at IOMUXC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) switch (imx6_pcie->drvdata->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case IMX6SX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) IMX6SX_GPR12_PCIE_PM_TURN_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) IMX6SX_GPR12_PCIE_PM_TURN_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(dev, "PME_Turn_Off not implemented\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * Components with an upstream port must respond to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * PME_Turn_Off with PME_TO_Ack but we can't check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * The standard recommends a 1-10ms timeout after which to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * proceed anyway as if acks were received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) pm_turnoff_sleep:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) usleep_range(1000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) clk_disable_unprepare(imx6_pcie->pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) clk_disable_unprepare(imx6_pcie->pcie_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) clk_disable_unprepare(imx6_pcie->pcie_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) switch (imx6_pcie->drvdata->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) case IMX6SX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) case IMX7D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) case IMX8MQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) clk_disable_unprepare(imx6_pcie->pcie_aux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static int imx6_pcie_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) imx6_pcie_pm_turnoff(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) imx6_pcie_clk_disable(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) imx6_pcie_ltssm_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static int imx6_pcie_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct pcie_port *pp = &imx6_pcie->pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) imx6_pcie_assert_core_reset(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) imx6_pcie_init_phy(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) imx6_pcie_deassert_core_reset(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) dw_pcie_setup_rc(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ret = imx6_pcie_establish_link(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dev_info(dev, "pcie link is down after resume.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static const struct dev_pm_ops imx6_pcie_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) imx6_pcie_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int imx6_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct imx6_pcie *imx6_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct resource *dbi_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (!imx6_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) pci->ops = &dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) imx6_pcie->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) imx6_pcie->drvdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* Find the PHY if one is defined, only imx7d uses it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ret = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dev_err(dev, "Unable to map PCIe PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (IS_ERR(imx6_pcie->phy_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) dev_err(dev, "Unable to map PCIe PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return PTR_ERR(imx6_pcie->phy_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (IS_ERR(pci->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* Fetch GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) imx6_pcie->gpio_active_high = of_property_read_bool(node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) "reset-gpio-active-high");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (gpio_is_valid(imx6_pcie->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) imx6_pcie->gpio_active_high ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) GPIOF_OUT_INIT_HIGH :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) GPIOF_OUT_INIT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) "PCIe reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev_err(dev, "unable to get reset gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return imx6_pcie->reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Fetch clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (IS_ERR(imx6_pcie->pcie_phy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) "pcie_phy clock source missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (IS_ERR(imx6_pcie->pcie_bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) "pcie_bus clock source missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) imx6_pcie->pcie = devm_clk_get(dev, "pcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (IS_ERR(imx6_pcie->pcie))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "pcie clock source missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) switch (imx6_pcie->drvdata->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case IMX6SX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) "pcie_inbound_axi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (IS_ERR(imx6_pcie->pcie_inbound_axi))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) "pcie_inbound_axi clock missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) case IMX8MQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (IS_ERR(imx6_pcie->pcie_aux))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "pcie_aux clock source missing or invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) case IMX7D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) imx6_pcie->controller_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "pciephy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (IS_ERR(imx6_pcie->pciephy_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dev_err(dev, "Failed to get PCIEPHY reset control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return PTR_ERR(imx6_pcie->pciephy_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) "apps");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (IS_ERR(imx6_pcie->apps_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) dev_err(dev, "Failed to get PCIE APPS reset control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return PTR_ERR(imx6_pcie->apps_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* Grab turnoff reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (IS_ERR(imx6_pcie->turnoff_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) dev_err(dev, "Failed to get TURNOFF reset control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return PTR_ERR(imx6_pcie->turnoff_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Grab GPR config register range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) imx6_pcie->iomuxc_gpr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) dev_err(dev, "unable to find iomuxc registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return PTR_ERR(imx6_pcie->iomuxc_gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* Grab PCIe PHY Tx Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) &imx6_pcie->tx_deemph_gen1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) imx6_pcie->tx_deemph_gen1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) &imx6_pcie->tx_deemph_gen2_3p5db))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) imx6_pcie->tx_deemph_gen2_3p5db = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) &imx6_pcie->tx_deemph_gen2_6db))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) imx6_pcie->tx_deemph_gen2_6db = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (of_property_read_u32(node, "fsl,tx-swing-full",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) &imx6_pcie->tx_swing_full))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) imx6_pcie->tx_swing_full = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (of_property_read_u32(node, "fsl,tx-swing-low",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) &imx6_pcie->tx_swing_low))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) imx6_pcie->tx_swing_low = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* Limit link speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) pci->link_gen = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret = of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (IS_ERR(imx6_pcie->vpcie)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return PTR_ERR(imx6_pcie->vpcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) imx6_pcie->vpcie = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) platform_set_drvdata(pdev, imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ret = imx6_pcie_attach_pd(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ret = imx6_add_pcie_port(imx6_pcie, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (pci_msi_enabled()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) val |= PCI_MSI_FLAGS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static void imx6_pcie_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* bring down link, so bootloader gets clean state in case of reboot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) imx6_pcie_assert_core_reset(imx6_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static const struct imx6_pcie_drvdata drvdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) [IMX6Q] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .variant = IMX6Q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .flags = IMX6_PCIE_FLAG_IMX6_PHY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .dbi_length = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) [IMX6SX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .variant = IMX6SX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .flags = IMX6_PCIE_FLAG_IMX6_PHY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) [IMX6QP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .variant = IMX6QP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .flags = IMX6_PCIE_FLAG_IMX6_PHY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) [IMX7D] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .variant = IMX7D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) [IMX8MQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .variant = IMX8MQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static const struct of_device_id imx6_pcie_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static struct platform_driver imx6_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .name = "imx6q-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .of_match_table = imx6_pcie_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .pm = &imx6_pcie_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .probe_type = PROBE_PREFER_ASYNCHRONOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .probe = imx6_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .shutdown = imx6_pcie_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static void imx6_pcie_quirk(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct pci_bus *bus = dev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct pcie_port *pp = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Bus parent is the PCI bridge, its parent is this platform driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (!bus->dev.parent || !bus->dev.parent->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Make sure we only quirk devices associated with this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (pci_is_root_bus(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * Limit config length to avoid the kernel reading beyond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * the register set and causing an abort on i.MX 6Quad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (imx6_pcie->drvdata->dbi_length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) dev->cfg_size = imx6_pcie->drvdata->dbi_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_info(&dev->dev, "Limiting cfg_size to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev->cfg_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static int __init imx6_pcie_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #ifdef CONFIG_ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * Since probe() can be deferred we need to make sure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * hook_fault_code is not called after __init memory is freed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * by kernel and since imx6q_pcie_abort_handler() is a no-op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * we can install the handler here without risking it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) * accessing some uninitialized driver state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) "external abort on non-linefetch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return platform_driver_register(&imx6_pcie_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) device_initcall(imx6_pcie_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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