^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Kishon Vijay Abraham I <kishon@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "../../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "pcie-designware.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* PCIe controller wrapper DRA7XX configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ERR_SYS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ERR_FATAL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ERR_NONFATAL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ERR_COR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ERR_AXI BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ERR_ECRC BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PME_TURN_OFF BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PME_TO_ACK BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PM_PME BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LINK_REQ_RST BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LINK_UP_EVT BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CFG_BME_EVT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CFG_MSE_EVT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define INTA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define INTB BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define INTC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define INTD BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MSI BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DEVICE_TYPE_EP 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DEVICE_TYPE_LEG_EP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DEVICE_TYPE_RC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LTSSM_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LINK_UP BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCIECTRL_TI_CONF_MSI_XMT 0x012c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MSI_REQ_GRANT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MSI_VECTOR_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCIE_1LANE_2LANE_SELECTION BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCIE_B1C0_MODE_SEL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCIE_B0_B1_TSYNCEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct dra7xx_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void __iomem *base; /* DT ti_conf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int phy_count; /* DT phy-names count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct phy **phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum dw_pcie_device_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct dra7xx_pcie_of_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enum dw_pcie_device_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 b1co_mode_sel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return readl(pcie->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) writel(value, pcie->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int dra7xx_pcie_link_up(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return !!(reg & LINK_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reg &= ~LTSSM_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (dw_pcie_link_up(pci)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(dev, "link is already up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg |= LTSSM_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) LEG_EP_INTERRUPTS | MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dra7xx_pcie_writel(dra7xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MSI | LEG_EP_INTERRUPTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) INTERRUPTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) INTERRUPTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dra7xx_pcie_enable_msi_interrupts(dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int dra7xx_pcie_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) dw_pcie_setup_rc(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dra7xx_pcie_establish_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dw_pcie_wait_for_link(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dw_pcie_msi_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dra7xx_pcie_enable_interrupts(dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) irq_set_chip_data(irq, domain->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct irq_domain_ops intx_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .map = dra7xx_pcie_intx_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .xlate = pci_irqd_intx_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int pos, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (index * MSI_REG_CTRL_BLOCK_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) while (pos != MAX_MSI_IRQS_PER_CTRL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) irq = irq_find_mapping(pp->irq_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) (index * MAX_MSI_IRQS_PER_CTRL) + pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static void dra7xx_pcie_handle_msi_irq(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int ret, i, count, num_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Need to make sure all MSI status bits read 0 before exiting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Else, new MSI IRQs are not registered by the wrapper. Have an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * upperbound for the loop and exit the IRQ in case of IRQ flood
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * to avoid locking up system in interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) for (i = 0; i < num_ctrls; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ret |= dra7xx_pcie_handle_msi(pp, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } while (ret && count <= 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (count > 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) dev_warn_ratelimited(pci->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "Too many MSI IRQs to handle\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct dra7xx_pcie *dra7xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct pcie_port *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 virq, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pp = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dra7xx = to_dra7xx_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dra7xx_pcie_handle_msi_irq(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case INTA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case INTB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case INTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case INTD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) for_each_set_bit(bit, ®, PCI_NUM_INTX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) virq = irq_find_mapping(dra7xx->irq_domain, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct dra7xx_pcie *dra7xx = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct dw_pcie *pci = dra7xx->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct dw_pcie_ep *ep = &pci->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (reg & ERR_SYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_dbg(dev, "System Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (reg & ERR_FATAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dev_dbg(dev, "Fatal Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (reg & ERR_NONFATAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_dbg(dev, "Non Fatal Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (reg & ERR_COR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_dbg(dev, "Correctable Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (reg & ERR_AXI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev_dbg(dev, "AXI tag lookup fatal Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (reg & ERR_ECRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) dev_dbg(dev, "ECRC Error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (reg & PME_TURN_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "Power Management Event Turn-Off message received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (reg & PME_TO_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "Power Management Turn-Off Ack message received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (reg & PM_PME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_dbg(dev, "PM Power Management Event message received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (reg & LINK_REQ_RST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_dbg(dev, "Link Request Reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (reg & LINK_UP_EVT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (dra7xx->mode == DW_PCIE_EP_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dw_pcie_ep_linkup(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_dbg(dev, "Link-up state change\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (reg & CFG_BME_EVT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (reg & CFG_MSE_EVT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!pcie_intc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_err(dev, "No PCIe Intc node found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) irq_set_chained_handler_and_data(pp->irq, dra7xx_pcie_msi_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) &intx_domain_ops, pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) of_node_put(pcie_intc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!dra7xx->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_err(dev, "Failed to get a INTx IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void dra7xx_pcie_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct pcie_port *pp = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u64 msi_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) msi_target = (u64)pp->msi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) msg->address_lo = lower_32_bits(msi_target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) msg->address_hi = upper_32_bits(msi_target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) msg->data = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) (int)d->hwirq, msg->address_hi, msg->address_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int dra7xx_pcie_msi_set_affinity(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) const struct cpumask *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void dra7xx_pcie_bottom_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct pcie_port *pp = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned int res, bit, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) raw_spin_lock_irqsave(&pp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pp->irq_mask[ctrl] |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pp->irq_mask[ctrl]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) raw_spin_unlock_irqrestore(&pp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static void dra7xx_pcie_bottom_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct pcie_port *pp = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int res, bit, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) raw_spin_lock_irqsave(&pp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pp->irq_mask[ctrl] &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pp->irq_mask[ctrl]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) raw_spin_unlock_irqrestore(&pp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static void dra7xx_pcie_bottom_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct pcie_port *pp = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int res, bit, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static struct irq_chip dra7xx_pci_msi_bottom_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .name = "DRA7XX-PCI-MSI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .irq_ack = dra7xx_pcie_bottom_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .irq_compose_msi_msg = dra7xx_pcie_setup_msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .irq_set_affinity = dra7xx_pcie_msi_set_affinity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .irq_mask = dra7xx_pcie_bottom_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .irq_unmask = dra7xx_pcie_bottom_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int dra7xx_pcie_msi_host_init(struct pcie_port *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u32 ctrl, num_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pp->msi_irq_chip = &dra7xx_pci_msi_bottom_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* Initialize IRQ Status array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pp->irq_mask[ctrl] = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pp->irq_mask[ctrl]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = dw_pcie_allocate_domains(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pp->msi_data = dma_map_single_attrs(dev, &pp->msi_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) sizeof(pp->msi_msg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DMA_FROM_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret = dma_mapping_error(dev, pp->msi_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dev_err(dev, "Failed to map MSI data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pp->msi_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dw_pcie_free_msi(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .host_init = dra7xx_pcie_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .msi_host_init = dra7xx_pcie_msi_host_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) enum pci_barno bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dw_pcie_ep_reset_bar(pci, bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 interrupt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) reg |= MSI_REQ_GRANT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) enum pci_epc_irq_type type, u16 interrupt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case PCI_EPC_IRQ_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dra7xx_pcie_raise_legacy_irq(dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) case PCI_EPC_IRQ_MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(pci->dev, "UNKNOWN IRQ type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static const struct pci_epc_features dra7xx_pcie_epc_features = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .linkup_notifier = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .msi_capable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .msix_capable = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const struct pci_epc_features*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dra7xx_pcie_get_features(struct dw_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return &dra7xx_pcie_epc_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const struct dw_pcie_ep_ops pcie_ep_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .ep_init = dra7xx_pcie_ep_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .raise_irq = dra7xx_pcie_raise_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .get_features = dra7xx_pcie_get_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct dw_pcie_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct dw_pcie *pci = dra7xx->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ep = &pci->ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ep->ops = &pcie_ep_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (IS_ERR(pci->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pci->dbi_base2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) devm_platform_ioremap_resource_byname(pdev, "ep_dbics2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (IS_ERR(pci->dbi_base2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return PTR_ERR(pci->dbi_base2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ep->phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) ep->addr_size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ret = dw_pcie_ep_init(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_err(dev, "failed to initialize endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct dw_pcie *pci = dra7xx->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct pcie_port *pp = &pci->pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct device *dev = pci->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pp->irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (pp->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return pp->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = dra7xx_pcie_init_irq_domain(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (IS_ERR(pci->dbi_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return PTR_ERR(pci->dbi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pp->ops = &dra7xx_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ret = dw_pcie_host_init(pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dev_err(dev, "failed to initialize host\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const struct dw_pcie_ops dw_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .start_link = dra7xx_pcie_establish_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .stop_link = dra7xx_pcie_stop_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .link_up = dra7xx_pcie_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int phy_count = dra7xx->phy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) while (phy_count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) phy_power_off(dra7xx->phy[phy_count]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) phy_exit(dra7xx->phy[phy_count]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int phy_count = dra7xx->phy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) for (i = 0; i < phy_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) goto err_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = phy_init(dra7xx->phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) goto err_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = phy_power_on(dra7xx->phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) phy_exit(dra7xx->phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) goto err_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) err_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) while (--i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) phy_power_off(dra7xx->phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) phy_exit(dra7xx->phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .mode = DW_PCIE_RC_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .mode = DW_PCIE_EP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const struct dra7xx_pcie_of_data dra746_pcie_rc_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .b1co_mode_sel_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .mode = DW_PCIE_RC_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static const struct dra7xx_pcie_of_data dra726_pcie_rc_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .b1co_mode_sel_mask = GENMASK(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .mode = DW_PCIE_RC_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const struct dra7xx_pcie_of_data dra746_pcie_ep_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .b1co_mode_sel_mask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .mode = DW_PCIE_EP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const struct dra7xx_pcie_of_data dra726_pcie_ep_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .b1co_mode_sel_mask = GENMASK(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .mode = DW_PCIE_EP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const struct of_device_id of_dra7xx_pcie_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .compatible = "ti,dra7-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .data = &dra7xx_pcie_rc_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .compatible = "ti,dra7-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .data = &dra7xx_pcie_ep_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .compatible = "ti,dra746-pcie-rc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .data = &dra746_pcie_rc_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .compatible = "ti,dra726-pcie-rc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .data = &dra726_pcie_rc_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .compatible = "ti,dra746-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .data = &dra746_pcie_ep_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .compatible = "ti,dra726-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .data = &dra726_pcie_ep_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * @dra7xx: the dra7xx device where the workaround should be applied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * Access to the PCIe slave port that are not 32-bit aligned will result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * 0x3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) regmap = syscon_regmap_lookup_by_phandle(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "ti,syscon-unaligned-access");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 2, 0, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = regmap_update_bits(regmap, args.args[0], args.args[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) args.args[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_err(dev, "failed to enable unaligned access\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) of_node_put(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int dra7xx_pcie_configure_two_lane(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 b1co_mode_sel_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct regmap *pcie_syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned int pcie_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) pcie_syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-lane-sel");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (IS_ERR(pcie_syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) dev_err(dev, "unable to get ti,syscon-lane-sel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (of_property_read_u32_index(np, "ti,syscon-lane-sel", 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) &pcie_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_err(dev, "couldn't get lane selection reg offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mask = b1co_mode_sel_mask | PCIE_B0_B1_TSYNCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) val = PCIE_B1C0_MODE_SEL | PCIE_B0_B1_TSYNCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) regmap_update_bits(pcie_syscon, pcie_reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int __init dra7xx_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int phy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct phy **phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct device_link **link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct dw_pcie *pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct dra7xx_pcie *dra7xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) char name[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct gpio_desc *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) const struct dra7xx_pcie_of_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) enum dw_pcie_device_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u32 b1co_mode_sel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) data = (struct dra7xx_pcie_of_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mode = (enum dw_pcie_device_mode)data->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) b1co_mode_sel_mask = data->b1co_mode_sel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (!dra7xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (!pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pci->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) pci->ops = &dw_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) base = devm_platform_ioremap_resource_byname(pdev, "ti_conf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) phy_count = of_property_count_strings(np, "phy-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (phy_count < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dev_err(dev, "unable to find the strings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return phy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) phy = devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (!link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) for (i = 0; i < phy_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) snprintf(name, sizeof(name), "pcie-phy%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) phy[i] = devm_phy_get(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (IS_ERR(phy[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return PTR_ERR(phy[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (!link[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) goto err_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dra7xx->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dra7xx->phy = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dra7xx->pci = pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dra7xx->phy_count = phy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (phy_count == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ret = dra7xx_pcie_configure_two_lane(dev, b1co_mode_sel_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = dra7xx_pcie_enable_phy(dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dev_err(dev, "failed to enable phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) platform_set_drvdata(pdev, dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(dev, "pm_runtime_get_sync failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (IS_ERR(reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ret = PTR_ERR(reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) goto err_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) reg &= ~LTSSM_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) case DW_PCIE_RC_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) goto err_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) DEVICE_TYPE_RC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ret = dra7xx_pcie_unaligned_memaccess(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) dev_err(dev, "WA for Errata i870 not applied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret = dra7xx_add_pcie_port(dra7xx, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) goto err_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) case DW_PCIE_EP_TYPE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) goto err_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) DEVICE_TYPE_EP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ret = dra7xx_pcie_unaligned_memaccess(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) goto err_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = dra7xx_add_pcie_ep(dra7xx, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) goto err_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) dev_err(dev, "INVALID device type %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dra7xx->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dev_err(dev, "failed to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) goto err_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) err_gpio:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) err_get_sync:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dra7xx_pcie_disable_phy(dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) err_link:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) device_link_del(link[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int dra7xx_pcie_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct dw_pcie *pci = dra7xx->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (dra7xx->mode != DW_PCIE_RC_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* clear MSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) val &= ~PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int dra7xx_pcie_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct dw_pcie *pci = dra7xx->pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (dra7xx->mode != DW_PCIE_RC_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* set MSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) val |= PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int dra7xx_pcie_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) dra7xx_pcie_disable_phy(dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static int dra7xx_pcie_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ret = dra7xx_pcie_enable_phy(dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) dev_err(dev, "failed to enable phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static void dra7xx_pcie_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) dra7xx_pcie_stop_link(dra7xx->pci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) ret = pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dev_dbg(dev, "pm_runtime_put_sync failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dra7xx_pcie_disable_phy(dra7xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dra7xx_pcie_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static struct platform_driver dra7xx_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .name = "dra7-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .of_match_table = of_dra7xx_pcie_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .pm = &dra7xx_pcie_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .shutdown = dra7xx_pcie_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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