Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) menu "DesignWare PCI Core Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 	depends on PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) config PCIE_DW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) config PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	select PCIE_DW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) config PCIE_DW_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	depends on PCI_ENDPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	select PCIE_DW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) config PCI_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) config PCI_DRA7XX_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	bool "TI DRA7xx PCIe controller Host Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	depends on SOC_DRA7XX || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	depends on OF && HAS_IOMEM && TI_PIPE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	select PCI_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	default y if SOC_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	  Enables support for the PCIe controller in the DRA7xx SoC to work in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	  host mode. There are two instances of PCIe controller in DRA7xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	  This controller can work either as EP or RC. In order to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	  host-specific features PCI_DRA7XX_HOST must be selected and in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	  to enable device-specific features PCI_DRA7XX_EP must be selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	  This uses the DesignWare core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) config PCI_DRA7XX_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	bool "TI DRA7xx PCIe controller Endpoint Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	depends on SOC_DRA7XX || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	depends on PCI_ENDPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	depends on OF && HAS_IOMEM && TI_PIPE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	select PCIE_DW_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	select PCI_DRA7XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	  Enables support for the PCIe controller in the DRA7xx SoC to work in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	  endpoint mode. There are two instances of PCIe controller in DRA7xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	  This controller can work either as EP or RC. In order to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	  host-specific features PCI_DRA7XX_HOST must be selected and in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	  to enable device-specific features PCI_DRA7XX_EP must be selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	  This uses the DesignWare core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) config PCIE_DW_PLAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) config PCIE_DW_PLAT_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	bool "Platform bus based DesignWare PCIe Controller - Host mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	depends on PCI && PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	select PCIE_DW_PLAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	  Enables support for the PCIe controller in the Designware IP to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	  work in host mode. There are two instances of PCIe controller in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	  Designware IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	  This controller can work either as EP or RC. In order to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	  host-specific features PCIE_DW_PLAT_HOST must be selected and in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	  order to enable device-specific features PCI_DW_PLAT_EP must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	  selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) config PCIE_DW_PLAT_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	depends on PCI && PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	depends on PCI_ENDPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	select PCIE_DW_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	select PCIE_DW_PLAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	  Enables support for the PCIe controller in the Designware IP to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	  work in endpoint mode. There are two instances of PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	  in Designware IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	  This controller can work either as EP or RC. In order to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	  host-specific features PCIE_DW_PLAT_HOST must be selected and in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	  order to enable device-specific features PCI_DW_PLAT_EP must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	  selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) config PCIE_DW_ROCKCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	tristate "Rockchip DesignWare PCIe controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	select PCIE_DW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	depends on ARCH_ROCKCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	  Enables support for the DW PCIe controller in the Rockchip SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) config PCIE_RK_THREADED_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	bool "Threaded initialize Rockchip DW based PCIe controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	depends on PCIE_DW_ROCKCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	  Enables threaded initialize Rockchip DW based PCIe controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) config PCIE_DW_DMATEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	bool "DesignWare PCIe DMA test"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	depends on PCIE_DW_ROCKCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	depends on !ROCKCHIP_PCIE_DMA_OBJ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	  Enables support for the DW PCIe controller DMA test.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) config PCI_EXYNOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	bool "Samsung Exynos PCIe controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	depends on SOC_EXYNOS5440 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) config PCI_IMX6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	bool "Freescale i.MX6/7/8 PCIe controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	depends on ARCH_MXC || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) config PCIE_SPEAR13XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	bool "STMicroelectronics SPEAr PCIe controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	depends on ARCH_SPEAR13XX || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	  Say Y here if you want PCIe support on SPEAr13XX SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) config PCI_KEYSTONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) config PCI_KEYSTONE_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	bool "PCI Keystone Host Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	select PCI_KEYSTONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	  Enables support for the PCIe controller in the Keystone SoC to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	  work in host mode. The PCI controller on Keystone is based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	  DesignWare hardware and therefore the driver re-uses the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	  DesignWare core functions to implement the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) config PCI_KEYSTONE_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	bool "PCI Keystone Endpoint Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	depends on PCI_ENDPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	select PCIE_DW_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	select PCI_KEYSTONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	  Enables support for the PCIe controller in the Keystone SoC to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	  work in endpoint mode. The PCI controller on Keystone is based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	  on DesignWare hardware and therefore the driver re-uses the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	  DesignWare core functions to implement the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) config PCI_LAYERSCAPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	bool "Freescale Layerscape PCIe controller - Host mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	  Say Y here if you want to enable PCIe controller support on Layerscape
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	  SoCs to work in Host mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	  This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	  determines which PCIe controller works in EP mode and which PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	  controller works in RC mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) config PCI_LAYERSCAPE_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	bool "Freescale Layerscape PCIe controller - Endpoint mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	depends on PCI_ENDPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	select PCIE_DW_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	  Say Y here if you want to enable PCIe controller support on Layerscape
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	  SoCs to work in Endpoint mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	  This controller can work either as EP or RC. The RCW[HOST_AGT_PEX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	  determines which PCIe controller works in EP mode and which PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	  controller works in RC mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) config PCI_HISI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	depends on OF && (ARM64 || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	select PCI_HOST_COMMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	  Say Y here if you want PCIe controller support on HiSilicon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	  Hip05 and Hip06 SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) config PCIE_QCOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	bool "Qualcomm PCIe controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	depends on OF && (ARCH_QCOM || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	  Say Y here to enable PCIe controller support on Qualcomm SoCs. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	  PCIe controller uses the DesignWare core plus Qualcomm-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	  hardware wrappers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) config PCIE_ARMADA_8K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	bool "Marvell Armada-8K PCIe controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	depends on ARCH_MVEBU || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	  Say Y here if you want to enable PCIe controller support on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	  Armada-8K SoCs. The PCIe controller on Armada-8K is based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	  DesignWare hardware and therefore the driver re-uses the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	  DesignWare core functions to implement the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) config PCIE_ARTPEC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) config PCIE_ARTPEC6_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	bool "Axis ARTPEC-6 PCIe controller Host Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	depends on MACH_ARTPEC6 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	select PCIE_ARTPEC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	  Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	  host mode. This uses the DesignWare core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) config PCIE_ARTPEC6_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	bool "Axis ARTPEC-6 PCIe controller Endpoint Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	depends on MACH_ARTPEC6 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	depends on PCI_ENDPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	select PCIE_DW_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	select PCIE_ARTPEC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	  Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	  endpoint mode. This uses the DesignWare core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) config PCIE_INTEL_GW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	bool "Intel Gateway PCIe host controller support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	depends on OF && (X86 || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	  Say 'Y' here to enable PCIe Host controller support on Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	  Gateway SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	  The PCIe controller uses the DesignWare core plus Intel-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	  hardware wrappers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) config PCIE_KIRIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	depends on OF && (ARM64 || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	bool "HiSilicon Kirin series SoCs PCIe controllers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	  Say Y here if you want PCIe controller support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	  on HiSilicon Kirin series SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) config PCIE_HISI_STB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	bool "HiSilicon STB SoCs PCIe controllers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	depends on ARCH_HISI || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	  Say Y here if you want PCIe controller support on HiSilicon STB SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) config PCI_MESON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	tristate "MESON PCIe controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	default m if ARCH_MESON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	  Say Y here if you want to enable PCI controller support on Amlogic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	  SoCs. The PCI controller on Amlogic is based on DesignWare hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	  and therefore the driver re-uses the DesignWare core functions to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	  implement the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) config PCIE_TEGRA194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	tristate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) config PCIE_TEGRA194_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	tristate "NVIDIA Tegra194 (and later) PCIe controller - Host Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	depends on ARCH_TEGRA_194_SOC || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	select PHY_TEGRA194_P2U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	select PCIE_TEGRA194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	  Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	  work in host mode. There are two instances of PCIe controllers in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	  Tegra194. This controller can work either as EP or RC. In order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	  enable host-specific features PCIE_TEGRA194_HOST must be selected and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	  in order to enable device-specific features PCIE_TEGRA194_EP must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	  selected. This uses the DesignWare core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) config PCIE_TEGRA194_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	tristate "NVIDIA Tegra194 (and later) PCIe controller - Endpoint Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	depends on ARCH_TEGRA_194_SOC || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	depends on PCI_ENDPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	select PCIE_DW_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	select PHY_TEGRA194_P2U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	select PCIE_TEGRA194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	  Enables support for the PCIe controller in the NVIDIA Tegra194 SoC to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	  work in host mode. There are two instances of PCIe controllers in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	  Tegra194. This controller can work either as EP or RC. In order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	  enable host-specific features PCIE_TEGRA194_HOST must be selected and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	  in order to enable device-specific features PCIE_TEGRA194_EP must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	  selected. This uses the DesignWare core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) config PCIE_UNIPHIER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	bool "Socionext UniPhier PCIe host controllers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	depends on ARCH_UNIPHIER || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	depends on OF && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	  Say Y here if you want PCIe host controller support on UniPhier SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	  This driver supports LD20 and PXs3 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) config PCIE_UNIPHIER_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	bool "Socionext UniPhier PCIe endpoint controllers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	depends on ARCH_UNIPHIER || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	depends on OF && HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	depends on PCI_ENDPOINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	select PCIE_DW_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	  Say Y here if you want PCIe endpoint controller support on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	  UniPhier SoCs. This driver supports Pro5 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) config PCIE_AL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	bool "Amazon Annapurna Labs PCIe controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	depends on OF && (ARM64 || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	depends on PCI_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	select PCIE_DW_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	  Say Y here to enable support of the Amazon's Annapurna Labs PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	  controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	  core plus Annapurna Labs proprietary hardware wrappers. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	  required only for DT-based platforms. ACPI platforms with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	  Annapurna Labs PCIe controller don't need to enable this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) endmenu