^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2017 Cadence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Cadence PCIe controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _PCIE_CADENCE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _PCIE_CADENCE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Parameters for the waiting for link up routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LINK_WAIT_MAX_RETRIES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define LINK_WAIT_USLEEP_MIN 90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LINK_WAIT_USLEEP_MAX 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Local Management Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CDNS_PCIE_LM_BASE 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Vendor ID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CDNS_PCIE_LM_ID_VENDOR(vid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CDNS_PCIE_LM_ID_SUBSYS(sub) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Root Port Requestor ID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CDNS_PCIE_LM_RP_RID_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CDNS_PCIE_LM_RP_RID_(rid) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Endpoint Bus and Device Number Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Endpoint Function f BAR b Configuration Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) (GENMASK(4, 0) << ((b) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) (GENMASK(7, 5) << ((b) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Endpoint Function Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Root Complex BAR Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* BAR control values applicable to both Endpoint Function and Root Complex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (((aperture) - 2) << ((bar) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Endpoint Function Registers (PCI configuration space for endpoint functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Root Port Registers (PCI configuration space for the root port function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CDNS_PCIE_RP_BASE 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CDNS_PCIE_RP_CAP_OFFSET 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Address Translation Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CDNS_PCIE_AT_BASE 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Region r Outbound AXI to PCIe Address Translation Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Region r Outbound AXI to PCIe Address Translation Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Region r Outbound PCIe Descriptor Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Bit 23 MUST be set in RC mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Region r Outbound PCIe Descriptor Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Region r AXI Region Base Address Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Region r AXI Region Base Address Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Root Port BAR Inbound PCIe to AXI Address Translation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* AXI link down register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* LTSSM Capabilities register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) enum cdns_pcie_rp_bar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) RP_BAR_UNDEFINED = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) RP_BAR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) RP_BAR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) RP_NO_BAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CDNS_PCIE_RP_MAX_IB 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct cdns_pcie_rp_ib_bar {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) bool free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Normal/Vendor specific message access: offset inside some outbound region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CDNS_PCIE_NORMAL_MSG_CODE(code) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CDNS_PCIE_MSG_NO_DATA BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct cdns_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum cdns_pcie_msg_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MSG_CODE_ASSERT_INTA = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MSG_CODE_ASSERT_INTB = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MSG_CODE_ASSERT_INTC = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MSG_CODE_ASSERT_INTD = 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MSG_CODE_DEASSERT_INTA = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MSG_CODE_DEASSERT_INTB = 0x25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MSG_CODE_DEASSERT_INTC = 0x26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MSG_CODE_DEASSERT_INTD = 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) enum cdns_pcie_msg_routing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Route to Root Complex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MSG_ROUTING_TO_RC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Use Address Routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MSG_ROUTING_BY_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Use ID Routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MSG_ROUTING_BY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Route as Broadcast Message from Root Complex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MSG_ROUTING_BCAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Local message; terminate at receiver (INTx messages) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MSG_ROUTING_LOCAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Gather & route to Root Complex (PME_TO_Ack message) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MSG_ROUTING_GATHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct cdns_pcie_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int (*start_link)(struct cdns_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void (*stop_link)(struct cdns_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) bool (*link_up)(struct cdns_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * struct cdns_pcie - private data for Cadence PCIe controller drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * @reg_base: IO mapped register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @mem_res: start/end offsets in the physical system memory to map PCI accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * @bus: In Root Complex mode, the bus number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * @ops: Platform specific ops to control various inputs from Cadence PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * wrapper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct cdns_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct resource *mem_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) bool is_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int phy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct phy **phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct device_link **link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const struct cdns_pcie_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @pcie: Cadence PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @dev: pointer to PCIe device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @cfg_res: start/end offsets in the physical system memory to map PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * configuration space accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * @cfg_base: IO mapped window to access the PCI configuration space of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * single function at a time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @vendor_id: PCI vendor ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @device_id: PCI device ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct cdns_pcie_rc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct cdns_pcie pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct resource *cfg_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) void __iomem *cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int quirk_retrain_flag:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int quirk_detect_quiet_flag:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * struct cdns_pcie_epf - Structure to hold info about endpoint function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct cdns_pcie_epf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * @pcie: Cadence PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * @max_regions: maximum number of regions supported by hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * @ob_region_map: bitmask of mapped outbound regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * @ob_addr: base addresses in the AXI bus where the outbound regions start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * dedicated outbound regions is mapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * @irq_cpu_addr: base address in the CPU space where a write access triggers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * the sending of a memory write (MSI) / normal message (legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * IRQ) TLP through the PCIe bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * dedicated outbound region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * @irq_pci_fn: the latest PCI function that has updated the mapping of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * the MSI/legacy IRQ dedicated outbound region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * @irq_pending: bitmask of asserted legacy IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * @lock: spin lock to disable interrupts while modifying PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * registers fields (RMW) accessible by both remote RC and EP to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * minimize time between read and write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * @epf: Structure to hold info about endpoint function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct cdns_pcie_ep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct cdns_pcie pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 max_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long ob_region_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) phys_addr_t *ob_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) phys_addr_t irq_phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void __iomem *irq_cpu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u64 irq_pci_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 irq_pci_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 irq_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* protect writing to PCI_STATUS while raising legacy interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct cdns_pcie_epf *epf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned int quirk_detect_quiet_flag:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) writel(value, pcie->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return readl(pcie->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int offset = (unsigned long)addr & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 val = readl(aligned_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!IS_ALIGNED((uintptr_t)addr, size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pr_warn("Address %p and size %d are not aligned\n", addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (size > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return (val >> (8 * offset)) & ((1 << (size * 8)) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int offset = (unsigned long)addr & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!IS_ALIGNED((uintptr_t)addr, size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pr_warn("Address %p and size %d are not aligned\n", addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (size > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) writel(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mask = ~(((1 << (size * 8)) - 1) << (offset * 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) val = readl(aligned_addr) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val |= value << (offset * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) writel(val, aligned_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Root Port register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) cdns_pcie_write_sz(addr, 0x1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 reg, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) cdns_pcie_write_sz(addr, 0x2, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return cdns_pcie_read_sz(addr, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Endpoint Function register access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) cdns_pcie_write_sz(addr, 0x1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 reg, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) cdns_pcie_write_sz(addr, 0x2, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u32 reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return cdns_pcie_read_sz(addr, 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static inline int cdns_pcie_start_link(struct cdns_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (pcie->ops->start_link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return pcie->ops->start_link(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (pcie->ops->stop_link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pcie->ops->stop_link(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (pcie->ops->link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return pcie->ops->link_up(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #ifdef CONFIG_PCIE_CADENCE_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int cdns_pcie_host_setup(struct cdns_pcie_rc *rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #ifdef CONFIG_PCIE_CADENCE_EP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 r, bool is_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u64 cpu_addr, u64 pci_addr, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u8 busnr, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 r, u64 cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) extern const struct dev_pm_ops cdns_pcie_pm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #endif /* _PCIE_CADENCE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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