^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cadence PCIe platform driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019, Cadence Design Systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Tom Joseph <tjoseph@cadence.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pcie-cadence.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CDNS_PLAT_CPU_TO_BUS_ADDR 0x0FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * struct cdns_plat_pcie - private data for this PCIe platform driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * @pcie: Cadence PCIe controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @is_rc: Set to 1 indicates the PCIe controller mode is Root Complex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * if 0 it is in Endpoint mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct cdns_plat_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct cdns_pcie *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) bool is_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct cdns_plat_pcie_of_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) bool is_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const struct of_device_id cdns_plat_pcie_of_match[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const struct cdns_pcie_ops cdns_plat_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .cpu_addr_fixup = cdns_plat_cpu_addr_fixup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int cdns_plat_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct cdns_plat_pcie_of_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct cdns_plat_pcie *cdns_plat_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct cdns_pcie_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct cdns_pcie_rc *rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int phy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool is_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) match = of_match_device(cdns_plat_pcie_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) data = (struct cdns_plat_pcie_of_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) is_rc = data->is_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pr_debug(" Started %s with is_rc: %d\n", __func__, is_rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) cdns_plat_pcie = devm_kzalloc(dev, sizeof(*cdns_plat_pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (!cdns_plat_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) platform_set_drvdata(pdev, cdns_plat_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (is_rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_HOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) rc = pci_host_bridge_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rc->pcie.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) rc->pcie.ops = &cdns_plat_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cdns_plat_pcie->pcie = &rc->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cdns_plat_pcie->is_rc = is_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev_err(dev, "failed to init phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev_err(dev, "pm_runtime_get_sync() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = cdns_pcie_host_setup(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_EP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ep->pcie.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ep->pcie.ops = &cdns_plat_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) cdns_plat_pcie->pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cdns_plat_pcie->is_rc = is_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dev_err(dev, "failed to init phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(dev, "pm_runtime_get_sync() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = cdns_pcie_ep_setup(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) err_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) err_get_sync:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) cdns_pcie_disable_phy(cdns_plat_pcie->pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) phy_count = cdns_plat_pcie->pcie->phy_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) while (phy_count--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) device_link_del(cdns_plat_pcie->pcie->link[phy_count]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void cdns_plat_pcie_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct cdns_pcie *pcie = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_dbg(dev, "pm_runtime_put_sync failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cdns_pcie_disable_phy(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct cdns_plat_pcie_of_data cdns_plat_pcie_host_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .is_rc = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct cdns_plat_pcie_of_data cdns_plat_pcie_ep_of_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .is_rc = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct of_device_id cdns_plat_pcie_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .compatible = "cdns,cdns-pcie-host",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .data = &cdns_plat_pcie_host_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .compatible = "cdns,cdns-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .data = &cdns_plat_pcie_ep_of_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct platform_driver cdns_plat_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .name = "cdns-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .of_match_table = cdns_plat_pcie_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .pm = &cdns_pcie_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .probe = cdns_plat_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .shutdown = cdns_plat_pcie_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) builtin_platform_driver(cdns_plat_pcie_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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