^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2017 Cadence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Cadence PCIe host controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/list_sort.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pcie-cadence.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static u64 bar_max_size[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) [RP_BAR0] = _ULL(128 * SZ_2G),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) [RP_BAR1] = SZ_2G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) [RP_NO_BAR] = _BITULL(63),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static u8 bar_aperture_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) [RP_BAR0] = 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) [RP_BAR1] = 0xF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct cdns_pcie *pcie = &rc->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int busn = bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 addr0, desc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (pci_is_root_bus(bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Only the root port (devfn == 0) is connected to this bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * All other PCI devices are behind some bridge hence on another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (devfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return pcie->reg_base + (where & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Check that the link is up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Clear AXI link-down status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Update Output registers for AXI region 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(busn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Configuration Type 0 or Type 1 access. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * The bus number was already set once for all in desc1 by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * cdns_pcie_host_init_address_translation().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (busn == bridge->busnr + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return rc->cfg_base + (where & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct pci_ops cdns_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .map_bus = cdns_pci_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .read = pci_generic_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .write = pci_generic_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Check if the link is up or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (cdns_pcie_link_up(pcie)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dev_info(dev, "Link up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int cdns_pcie_retrain(struct cdns_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 lnk_stat, lnk_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Set retrain bit if current speed is 2.5 GB/s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * but the PCIe root port support is > 2.5 GB/s.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PCI_EXP_LNKCAP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) lnk_ctl = cdns_pcie_rp_readw(pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pcie_cap_off + PCI_EXP_LNKCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) lnk_ctl |= PCI_EXP_LNKCTL_RL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) lnk_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ret = cdns_pcie_host_wait_for_link(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct cdns_pcie *pcie = &rc->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = cdns_pcie_host_wait_for_link(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Retrain link for Gen2 training defect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * if quirk flag is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!ret && rc->quirk_retrain_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ret = cdns_pcie_retrain(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct cdns_pcie *pcie = &rc->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 value, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Set the root complex BAR configuration register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * - disable both BAR0 and BAR1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * - enable Prefetchable Memory Base and Limit registers in type 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * config space (64 bits).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * - enable IO Base and Limit registers in type 1 config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * space (32 bits).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) value = CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Set root port configuration space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (rc->vendor_id != 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) id = CDNS_PCIE_LM_ID_VENDOR(rc->vendor_id) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) CDNS_PCIE_LM_ID_SUBSYS(rc->vendor_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (rc->device_id != 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cdns_pcie_rp_writeb(pcie, PCI_CLASS_REVISION, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) enum cdns_pcie_rp_bar bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u64 cpu_addr, u64 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct cdns_pcie *pcie = &rc->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 addr0, addr1, aperture, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!rc->avail_ib_bar[bar])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rc->avail_ib_bar[bar] = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) aperture = ilog2(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) addr0 = CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(aperture) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (lower_32_bits(cpu_addr) & GENMASK(31, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) addr1 = upper_32_bits(cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar), addr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar), addr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (bar == RP_NO_BAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) value = cdns_pcie_readl(pcie, CDNS_PCIE_LM_RC_BAR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) value &= ~(LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (size + cpu_addr >= SZ_4G) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!(flags & IORESOURCE_PREFETCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) value |= LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!(flags & IORESOURCE_PREFETCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) value |= LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) value |= LM_RC_BAR_CFG_APERTURE(bar, aperture);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static enum cdns_pcie_rp_bar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum cdns_pcie_rp_bar bar, sel_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) sel_bar = RP_BAR_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!rc->avail_ib_bar[bar])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (size <= bar_max_size[bar]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (sel_bar == RP_BAR_UNDEFINED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) sel_bar = bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (bar_max_size[bar] < bar_max_size[sel_bar])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sel_bar = bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return sel_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static enum cdns_pcie_rp_bar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) enum cdns_pcie_rp_bar bar, sel_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) sel_bar = RP_BAR_UNDEFINED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!rc->avail_ib_bar[bar])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (size >= bar_max_size[bar]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (sel_bar == RP_BAR_UNDEFINED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sel_bar = bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (bar_max_size[bar] > bar_max_size[sel_bar])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sel_bar = bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return sel_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct resource_entry *entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u64 cpu_addr, pci_addr, size, winsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct cdns_pcie *pcie = &rc->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) enum cdns_pcie_rp_bar bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cpu_addr = entry->res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pci_addr = entry->res->start - entry->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) flags = entry->res->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) size = resource_size(entry->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (entry->offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_err(dev, "PCI addr: %llx must be equal to CPU addr: %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pci_addr, cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) while (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Try to find a minimum BAR whose size is greater than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * or equal to the remaining resource_entry size. This will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * fail if the size of each of the available BARs is less than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * the remaining resource_entry size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * If a minimum BAR is found, IB ATU will be configured and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * exited.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) bar = cdns_pcie_host_find_min_bar(rc, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (bar != RP_BAR_UNDEFINED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) size, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev_err(dev, "IB BAR: %d config failed\n", bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * If the control reaches here, it would mean the remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * resource_entry size cannot be fitted in a single BAR. So we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * find a maximum BAR whose size is less than or equal to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * remaining resource_entry size and split the resource entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * so that part of resource entry is fitted inside the maximum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * BAR. The remaining size would be fitted during the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * iteration of the loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * If a maximum BAR is not found, there is no way we can fit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * this resource_entry, so we error out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) bar = cdns_pcie_host_find_max_bar(rc, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (bar == RP_BAR_UNDEFINED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_err(dev, "No free BAR to map cpu_addr %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) winsize = bar_max_size[bar];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, winsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_err(dev, "IB BAR: %d config failed\n", bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) size -= winsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) cpu_addr += winsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int cdns_pcie_host_dma_ranges_cmp(void *priv, struct list_head *a, struct list_head *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct resource_entry *entry1, *entry2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) entry1 = container_of(a, struct resource_entry, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) entry2 = container_of(b, struct resource_entry, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return resource_size(entry2->res) - resource_size(entry1->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct cdns_pcie *pcie = &rc->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct resource_entry *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 no_bar_nbits = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bridge = pci_host_bridge_from_priv(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (list_empty(&bridge->dma_ranges)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) of_property_read_u32(np, "cdns,no-bar-match-nbits",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) &no_bar_nbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) err = cdns_pcie_host_bar_ib_config(rc, RP_NO_BAR, 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (u64)1 << no_bar_nbits, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) resource_list_for_each_entry(entry, &bridge->dma_ranges) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) err = cdns_pcie_host_bar_config(rc, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_err(dev, "Fail to configure IB using dma-ranges\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct cdns_pcie *pcie = &rc->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct resource *cfg_res = rc->cfg_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct resource_entry *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u64 cpu_addr = cfg_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 addr0, addr1, desc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int r, busnr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) entry = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) busnr = entry->res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Reserve region 0 for PCI configure space accesses:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * cdns_pci_map_bus(), other region registers are set here once for all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) addr1 = 0; /* Should be programmed to zero. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(busnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (pcie->ops->cpu_addr_fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) (lower_32_bits(cpu_addr) & GENMASK(31, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) addr1 = upper_32_bits(cpu_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) r = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) resource_list_for_each_entry(entry, &bridge->windows) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct resource *res = entry->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u64 pci_addr = res->start - entry->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (resource_type(res) == IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) cdns_pcie_set_outbound_region(pcie, busnr, 0, r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pci_pio_to_address(res->start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pci_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) cdns_pcie_set_outbound_region(pcie, busnr, 0, r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pci_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) r++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return cdns_pcie_host_map_dma_ranges(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static int cdns_pcie_host_init(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct cdns_pcie_rc *rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) err = cdns_pcie_host_init_root_port(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return cdns_pcie_host_init_address_translation(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct device *dev = rc->pcie.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) enum cdns_pcie_rp_bar bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct cdns_pcie *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) bridge = pci_host_bridge_from_priv(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pcie = &rc->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pcie->is_rc = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) rc->vendor_id = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) of_property_read_u32(np, "vendor-id", &rc->vendor_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) rc->device_id = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) of_property_read_u32(np, "device-id", &rc->device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (IS_ERR(pcie->reg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_err(dev, "missing \"reg\"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return PTR_ERR(pcie->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) rc->cfg_base = devm_pci_remap_cfg_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (IS_ERR(rc->cfg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return PTR_ERR(rc->cfg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) rc->cfg_res = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (rc->quirk_detect_quiet_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ret = cdns_pcie_start_link(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_err(dev, "Failed to start link\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = cdns_pcie_host_start_link(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_dbg(dev, "PCIe link never came up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) rc->avail_ib_bar[bar] = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ret = cdns_pcie_host_init(dev, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!bridge->ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) bridge->ops = &cdns_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = pci_host_probe(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) err_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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