^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2017 Cadence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Cadence PCIe endpoint controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci-epc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pcie-cadence.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct pci_epf_header *hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) hdr->subclass_code | hdr->baseclass_code << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) hdr->cache_line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Vendor ID can only be modified from function 0, all other functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * use the same vendor ID as function 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (fn == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Update the vendor IDs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct pci_epf_bar *epf_bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct cdns_pcie_epf *epf = &ep->epf[fn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dma_addr_t bar_phys = epf_bar->phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum pci_barno bar = epf_bar->barno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int flags = epf_bar->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u64 sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* BAR size is 2^(aperture + 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * roundup_pow_of_two() returns an unsigned long, which is not suited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * for 64bit values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) sz = 1ULL << fls64(sz - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bool is_64bits = sz > SZ_2G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (is_64bits && (bar & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (is_64bits && is_prefetch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) else if (is_prefetch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else if (is_64bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) addr0 = lower_32_bits(bar_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) addr1 = upper_32_bits(bar_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) addr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) addr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (bar < BAR_4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) b = bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) b = bar - BAR_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) cfg = cdns_pcie_readl(pcie, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) cdns_pcie_writel(pcie, reg, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) epf->epf_bar[bar] = epf_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct pci_epf_bar *epf_bar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct cdns_pcie_epf *epf = &ep->epf[fn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) enum pci_barno bar = epf_bar->barno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 reg, cfg, b, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (bar < BAR_4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) b = bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) b = bar - BAR_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) cfg = cdns_pcie_readl(pcie, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) cdns_pcie_writel(pcie, reg, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) epf->epf_bar[bar] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u64 pci_addr, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) r = find_first_zero_bit(&ep->ob_region_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) sizeof(ep->ob_region_map) * BITS_PER_LONG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (r >= ep->max_regions - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(&epc->dev, "no free outbound region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cdns_pcie_set_outbound_region(pcie, 0, fn, r, false, addr, pci_addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) set_bit(r, &ep->ob_region_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ep->ob_addr[r] = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) phys_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) for (r = 0; r < ep->max_regions - 1; r++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ep->ob_addr[r] == addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (r == ep->max_regions - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) cdns_pcie_reset_outbound_region(pcie, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ep->ob_addr[r] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clear_bit(r, &ep->ob_region_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * Set the Multiple Message Capable bitfield into the Message Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) flags |= PCI_MSI_FLAGS_64BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) flags &= ~PCI_MSI_FLAGS_MASKBIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u16 flags, mme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Validate that the MSI feature is actually enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!(flags & PCI_MSI_FLAGS_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * Get the Multiple Message Enable bitfield from the Message Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return mme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reg = cap + PCI_MSIX_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) val = cdns_pcie_ep_fn_readw(pcie, func_no, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!(val & PCI_MSIX_FLAGS_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) val &= PCI_MSIX_FLAGS_QSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u16 interrupts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum pci_barno bir, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) reg = cap + PCI_MSIX_FLAGS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val = cdns_pcie_ep_fn_readw(pcie, fn, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val &= ~PCI_MSIX_FLAGS_QSIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) val |= interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cdns_pcie_ep_fn_writew(pcie, fn, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Set MSIX BAR and offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) reg = cap + PCI_MSIX_TABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) val = offset | bir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Set PBA BAR and offset. BAR must match MSIX BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) reg = cap + PCI_MSIX_PBA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) cdns_pcie_ep_fn_writel(pcie, fn, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u8 intx, bool is_asserted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u8 msg_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) intx &= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Set the outbound region if needed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ep->irq_pci_fn != fn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* First region was reserved for IRQ writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cdns_pcie_set_outbound_region_for_normal_msg(pcie, 0, fn, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ep->irq_phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ep->irq_pci_fn = fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (is_asserted) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ep->irq_pending |= BIT(intx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) msg_code = MSG_CODE_ASSERT_INTA + intx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ep->irq_pending &= ~BIT(intx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) msg_code = MSG_CODE_DEASSERT_INTA + intx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) spin_lock_irqsave(&ep->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) status ^= PCI_STATUS_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spin_unlock_irqrestore(&ep->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) CDNS_PCIE_MSG_NO_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writel(0, ep->irq_cpu_addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (cmd & PCI_COMMAND_INTX_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) cdns_pcie_ep_assert_intx(ep, fn, intx, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) cdns_pcie_ep_assert_intx(ep, fn, intx, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 interrupt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u16 flags, mme, data, data_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u8 msi_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u64 pci_addr, pci_addr_mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Check whether the MSI feature has been enabled by the PCI host. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!(flags & PCI_MSI_FLAGS_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Get the number of enabled MSIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) msi_count = 1 << mme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!interrupt_num || interrupt_num > msi_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Compute the data value to be written. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) data_mask = msi_count - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Get the PCI address where to write the data into. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pci_addr <<= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pci_addr &= GENMASK_ULL(63, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Set the outbound region if needed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ep->irq_pci_fn != fn)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* First region was reserved for IRQ writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) cdns_pcie_set_outbound_region(pcie, 0, fn, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ep->irq_phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pci_addr & ~pci_addr_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pci_addr_mask + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ep->irq_pci_fn = fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u16 interrupt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 cap = CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32 tbl_offset, msg_data, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct pci_epf_msix_tbl *msix_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct cdns_pcie_epf *epf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u64 pci_addr_mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u64 msg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u8 bir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Check whether the MSI-X feature has been enabled by the PCI host. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!(flags & PCI_MSIX_FLAGS_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) reg = cap + PCI_MSIX_TABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) tbl_offset = cdns_pcie_ep_fn_readl(pcie, fn, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) bir = tbl_offset & PCI_MSIX_TABLE_BIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) tbl_offset &= PCI_MSIX_TABLE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) epf = &ep->epf[fn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) msix_tbl = epf->epf_bar[bir]->addr + tbl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) msg_addr = msix_tbl[(interrupt_num - 1)].msg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) msg_data = msix_tbl[(interrupt_num - 1)].msg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Set the outbound region if needed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (ep->irq_pci_addr != (msg_addr & ~pci_addr_mask) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ep->irq_pci_fn != fn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* First region was reserved for IRQ writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) cdns_pcie_set_outbound_region(pcie, 0, fn, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ep->irq_phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) msg_addr & ~pci_addr_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pci_addr_mask + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ep->irq_pci_addr = (msg_addr & ~pci_addr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ep->irq_pci_fn = fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) enum pci_epc_irq_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u16 interrupt_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case PCI_EPC_IRQ_LEGACY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return cdns_pcie_ep_send_legacy_irq(ep, fn, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case PCI_EPC_IRQ_MSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case PCI_EPC_IRQ_MSIX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return cdns_pcie_ep_send_msix_irq(ep, fn, interrupt_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int cdns_pcie_ep_start(struct pci_epc *epc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct pci_epf *epf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * BIT(0) is hardwired to 1, hence function 0 is always enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * and can't be disabled anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) cfg = BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) list_for_each_entry(epf, &epc->pci_epf, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) cfg |= BIT(epf->func_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = cdns_pcie_start_link(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_err(dev, "Failed to start link\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const struct pci_epc_features cdns_pcie_epc_features = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .linkup_notifier = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .msi_capable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .msix_capable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const struct pci_epc_features*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return &cdns_pcie_epc_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct pci_epc_ops cdns_pcie_epc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .write_header = cdns_pcie_ep_write_header,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .set_bar = cdns_pcie_ep_set_bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .clear_bar = cdns_pcie_ep_clear_bar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .map_addr = cdns_pcie_ep_map_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .unmap_addr = cdns_pcie_ep_unmap_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .set_msi = cdns_pcie_ep_set_msi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .get_msi = cdns_pcie_ep_get_msi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .set_msix = cdns_pcie_ep_set_msix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .get_msix = cdns_pcie_ep_get_msix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .raise_irq = cdns_pcie_ep_raise_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .start = cdns_pcie_ep_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .get_features = cdns_pcie_ep_get_features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct device *dev = ep->pcie.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct cdns_pcie *pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct pci_epc *epc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pcie->is_rc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pcie->reg_base = devm_platform_ioremap_resource_byname(pdev, "reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (IS_ERR(pcie->reg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_err(dev, "missing \"reg\"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return PTR_ERR(pcie->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_err(dev, "missing \"mem\"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pcie->mem_res = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = of_property_read_u32(np, "cdns,max-outbound-regions",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) &ep->max_regions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dev_err(dev, "missing \"cdns,max-outbound-regions\"\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ep->ob_addr = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ep->max_regions, sizeof(*ep->ob_addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!ep->ob_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (IS_ERR(epc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(dev, "failed to create epc device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return PTR_ERR(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) epc_set_drvdata(epc, ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) epc->max_functions = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ep->epf = devm_kcalloc(dev, epc->max_functions, sizeof(*ep->epf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!ep->epf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = pci_epc_mem_init(epc, pcie->mem_res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) resource_size(pcie->mem_res), PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_err(dev, "failed to initialize the memory space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) SZ_128K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!ep->irq_cpu_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_err(dev, "failed to reserve memory space for MSI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) goto free_epc_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Reserve region 0 for IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) set_bit(0, &ep->ob_region_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ep->quirk_detect_quiet_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) cdns_pcie_detect_quiet_min_delay_set(&ep->pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) spin_lock_init(&ep->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) free_epc_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) pci_epc_mem_exit(epc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags