^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pci-j721e - PCIe controller driver for TI's J721E SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Kishon Vijay Abraham I <kishon@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../../pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pcie-cadence.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ENABLE_REG_SYS_2 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STATUS_REG_SYS_2 0x508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STATUS_CLR_REG_SYS_2 0x708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LINK_DOWN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define J7200_LINK_DOWN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define J721E_PCIE_USER_CMD_STATUS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LINK_TRAINING_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define J721E_PCIE_USER_LINKSTATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LINK_STATUS GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum link_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) NO_RECEIVERS_DETECTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) LINK_TRAINING_IN_PROGRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) LINK_UP_DL_IN_PROGRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) LINK_UP_DL_COMPLETED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define J721E_MODE_RC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LANE_COUNT_MASK BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LANE_COUNT(n) ((n) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GENERATION_SEL_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct j721e_pcie {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct cdns_pcie *cdns_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *user_cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) void __iomem *intd_cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 linkdown_irq_regfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum j721e_pcie_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PCI_MODE_RC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PCI_MODE_EP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct j721e_pcie_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum j721e_pcie_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int quirk_retrain_flag:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int quirk_detect_quiet_flag:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 linkdown_irq_regfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int byte_access_allowed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return readl(pcie->user_cfg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) writel(value, pcie->user_cfg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return readl(pcie->intd_cfg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel(value, pcie->intd_cfg_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct j721e_pcie *pcie = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!(reg & pcie->linkdown_irq_regfield))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_err(dev, "LINK DOWN!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg |= pcie->linkdown_irq_regfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) reg |= LINK_TRAINING_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) reg &= ~LINK_TRAINING_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg &= LINK_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (reg == LINK_UP_DL_COMPLETED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const struct cdns_pcie_ops j721e_pcie_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .start_link = j721e_pcie_start_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .stop_link = j721e_pcie_stop_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .link_up = j721e_pcie_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 mask = J721E_MODE_RC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 mode = pcie->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (mode == PCI_MODE_RC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) val = J721E_MODE_RC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = regmap_update_bits(syscon, 0, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(dev, "failed to set pcie mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct regmap *syscon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int link_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) link_speed = of_pci_get_max_link_speed(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (link_speed < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) link_speed = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val = link_speed - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(dev, "failed to set link speed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct regmap *syscon)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 lanes = pcie->num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) val = LANE_COUNT(lanes - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(dev, "failed to set link count\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct device *dev = pcie->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct regmap *syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (IS_ERR(syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return PTR_ERR(syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = j721e_pcie_set_mode(pcie, syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_err(dev, "Failed to set pci mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = j721e_pcie_set_link_speed(pcie, syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(dev, "Failed to set link speed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = j721e_pcie_set_lane_count(pcie, syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) dev_err(dev, "Failed to set num-lanes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int where, int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (pci_is_root_bus(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return pci_generic_config_read32(bus, devfn, where, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return pci_generic_config_read(bus, devfn, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (pci_is_root_bus(bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return pci_generic_config_write32(bus, devfn, where, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return pci_generic_config_write(bus, devfn, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct pci_ops cdns_ti_pcie_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .map_bus = cdns_pci_map_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .read = cdns_ti_pcie_config_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .write = cdns_ti_pcie_config_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct j721e_pcie_data j721e_pcie_rc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .mode = PCI_MODE_RC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .quirk_retrain_flag = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .byte_access_allowed = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .linkdown_irq_regfield = LINK_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct j721e_pcie_data j721e_pcie_ep_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .mode = PCI_MODE_EP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .linkdown_irq_regfield = LINK_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct j721e_pcie_data j7200_pcie_rc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .mode = PCI_MODE_RC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .quirk_detect_quiet_flag = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .linkdown_irq_regfield = J7200_LINK_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .byte_access_allowed = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct j721e_pcie_data j7200_pcie_ep_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .mode = PCI_MODE_EP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .quirk_detect_quiet_flag = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct j721e_pcie_data am64_pcie_rc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .mode = PCI_MODE_RC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .linkdown_irq_regfield = J7200_LINK_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .byte_access_allowed = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct j721e_pcie_data am64_pcie_ep_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .mode = PCI_MODE_EP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .linkdown_irq_regfield = J7200_LINK_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct of_device_id of_j721e_pcie_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .compatible = "ti,j721e-pcie-host",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .data = &j721e_pcie_rc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .compatible = "ti,j721e-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .data = &j721e_pcie_ep_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .compatible = "ti,j7200-pcie-host",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .data = &j7200_pcie_rc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .compatible = "ti,j7200-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .data = &j7200_pcie_ep_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .compatible = "ti,am64-pcie-host",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .data = &am64_pcie_rc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .compatible = "ti,am64-pcie-ep",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .data = &am64_pcie_ep_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int j721e_pcie_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct j721e_pcie_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct cdns_pcie *cdns_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct j721e_pcie *pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct cdns_pcie_rc *rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct cdns_pcie_ep *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct gpio_desc *gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) data = (struct j721e_pcie_data *)of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mode = (u32)data->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!pcie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) pcie->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pcie->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pcie->linkdown_irq_regfield = data->linkdown_irq_regfield;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pcie->intd_cfg_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pcie->user_cfg_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = of_property_read_u32(node, "num-lanes", &num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ret || num_lanes > MAX_LANES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) num_lanes = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) pcie->num_lanes = num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) irq = platform_get_irq_byname(pdev, "link_state");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_set_drvdata(dev, pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_err(dev, "pm_runtime_get_sync failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = j721e_pcie_ctrl_init(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_err(dev, "pm_runtime_get_sync failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "j721e-pcie-link-down-irq", pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dev_err(dev, "failed to request link state IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) j721e_pcie_config_link_irq(pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case PCI_MODE_RC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!bridge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!data->byte_access_allowed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) bridge->ops = &cdns_ti_pcie_host_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) rc = pci_host_bridge_priv(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) rc->quirk_retrain_flag = data->quirk_retrain_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) cdns_pcie = &rc->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) cdns_pcie->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) cdns_pcie->ops = &j721e_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pcie->cdns_pcie = cdns_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (IS_ERR(gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = PTR_ERR(gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dev_err(dev, "Failed to get reset GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = cdns_pcie_init_phy(dev, cdns_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(dev, "Failed to init phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * "Power Sequencing and Reset Signal Timings" table in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * indicates PERST# should be deasserted after minimum of 100us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * once REFCLK is stable. The REFCLK to the connector in RC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * mode is selected while enabling the PHY. So deassert PERST#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * after 100 us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) gpiod_set_value_cansleep(gpiod, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = cdns_pcie_host_setup(rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) goto err_pcie_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case PCI_MODE_EP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (!ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) cdns_pcie = &ep->pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) cdns_pcie->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) cdns_pcie->ops = &j721e_pcie_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) pcie->cdns_pcie = cdns_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = cdns_pcie_init_phy(dev, cdns_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(dev, "Failed to init phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) goto err_get_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = cdns_pcie_ep_setup(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto err_pcie_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_err(dev, "INVALID device type %d\n", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) err_pcie_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cdns_pcie_disable_phy(cdns_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) err_get_sync:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int j721e_pcie_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct j721e_pcie *pcie = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) cdns_pcie_disable_phy(cdns_pcie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct platform_driver j721e_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .probe = j721e_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .remove = j721e_pcie_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .name = "j721e-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .of_match_table = of_j721e_pcie_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) builtin_platform_driver(j721e_pcie_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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