^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _MULTIFACE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _MULTIFACE_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Defines for SerialMaster, Multiface Card II and Multiface Card III
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * The addresses given below are offsets to the board base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 6.11.95 Joerg Dorchain (dorchain@mpi-sb.mpg.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PIA_REG_PADWIDTH 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DUARTBASE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PITBASE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ROMBASE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PIABASE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)