^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ** System Bus Adapter (SBA) I/O MMU manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) ** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) ** (c) Copyright 2000-2004 Hewlett-Packard Company
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ** This module initializes the IOC (I/O Controller) found on B1000/C3000/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ** J5000/J7000/N-class/L-class machines and their successors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ** FIXME: add DMA hint support programming in both sba and lba modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/dma-map-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/iommu-helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/dma.h> /* for DMA_CHUNK_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/hardware.h> /* for register_parisc_driver() stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/ropes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/mckinley.h> /* for proc_mckinley_root */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/runway.h> /* for proc_runway_root */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/page.h> /* for PAGE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/pdc.h> /* for PDC_MODEL_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/pdcpat.h> /* for is_pdc_pat() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/parisc-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "iommu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MODULE_NAME "SBA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ** The number of debug flags is a clue - this code is fragile.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ** Don't even think about messing with it unless you have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ** plenty of 710's to sacrifice to the computer gods. :^)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #undef DEBUG_SBA_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #undef DEBUG_SBA_RUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #undef DEBUG_SBA_RUN_SG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #undef DEBUG_SBA_RESOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #undef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #undef DEBUG_LARGE_SG_ENTRIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #undef DEBUG_DMB_TRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifdef DEBUG_SBA_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DBG_INIT(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DBG_INIT(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #ifdef DEBUG_SBA_RUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DBG_RUN(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DBG_RUN(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifdef DEBUG_SBA_RUN_SG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DBG_RUN_SG(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DBG_RUN_SG(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifdef DEBUG_SBA_RESOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DBG_RES(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DBG_RES(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SBA_INLINE __inline__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DEFAULT_DMA_HINT_REG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct sba_device *sba_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) EXPORT_SYMBOL_GPL(sba_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static unsigned long ioc_needs_fdc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* global count of IOMMUs in the system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static unsigned int global_ioc_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* PA8700 (Piranha 2.2) bug workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static unsigned long piranha_bad_128k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Looks nice and keeps the compiler happy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SBA_DEV(d) ((struct sba_device *) (d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef CONFIG_AGP_PARISC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SBA_AGP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif /*CONFIG_AGP_PARISC*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #ifdef SBA_AGP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int sba_reserve_agpgart = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) module_param(sba_reserve_agpgart, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ** SBA register read and write support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ** BE WARNED: register writes are posted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ** (ie follow writes which must reach HW with a read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ** Superdome (in particular, REO) allows only 64-bit CSR accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define READ_REG32(addr) readl(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define READ_REG64(addr) readq(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define WRITE_REG32(val, addr) writel((val), (addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define WRITE_REG64(val, addr) writeq((val), (addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define READ_REG(addr) READ_REG64(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define WRITE_REG(value, addr) WRITE_REG64(value, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define READ_REG(addr) READ_REG32(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define WRITE_REG(value, addr) WRITE_REG32(value, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #ifdef DEBUG_SBA_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * sba_dump_ranges - debugging only - print ranges assigned to this IOA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @hpa: base address of the sba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * IO Adapter (aka Bus Converter).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) sba_dump_ranges(void __iomem *hpa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DBG_INIT("SBA at 0x%p\n", hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DBG_INIT("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * sba_dump_tlb - debugging only - print IOMMU operating parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @hpa: base address of the IOMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Print the size/location of the IO MMU PDIR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void sba_dump_tlb(void __iomem *hpa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DBG_INIT("IO TLB at 0x%p\n", hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DBG_INIT("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define sba_dump_ranges(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define sba_dump_tlb(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif /* DEBUG_SBA_INIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #ifdef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @ioc: IO MMU structure which owns the pdir we are interested in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @msg: text to print ont the output line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @pide: pdir index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Print one entry of the IO MMU PDIR in human readable form.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* start printing from lowest pde in rval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) uint rcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rptr, pide & (BITS_PER_LONG - 1), *rptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) while (rcnt < BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) printk(KERN_DEBUG "%s %2d %p %016Lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) (rcnt == (pide & (BITS_PER_LONG - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ? " -->" : " ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rcnt, ptr, *ptr );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) rcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) printk(KERN_DEBUG "%s", msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * sba_check_pdir - debugging only - consistency checker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @ioc: IO MMU structure which owns the pdir we are interested in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @msg: text to print ont the output line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Verify the resource map and pdir state is consistent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) sba_check_pdir(struct ioc *ioc, char *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u64 *pptr = ioc->pdir_base; /* pdir ptr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) uint pide = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) while (rptr < rptr_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 rval = *rptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int rcnt = 32; /* number of bits we might check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) while (rcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Get last byte and highest bit from that */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 pde = ((u32) (((char *)pptr)[7])) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if ((rval ^ pde) & 0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ** BUMMER! -- res_map != pdir --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ** Dump rval and matching pdir entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) sba_dump_pdir_entry(ioc, msg, pide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rcnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rval <<= 1; /* try the next bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pide++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) rptr++; /* look at next word of res_map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* It'd be nice if we always got here :^) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * sba_dump_sg - debugging only - print Scatter-Gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @ioc: IO MMU structure which owns the pdir we are interested in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @startsg: head of the SG list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @nents: number of entries in SG list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * print the SG list so we can verify it's correct by hand.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) while (nents-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (unsigned long) sg_dma_address(startsg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) sg_dma_len(startsg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) sg_virt(startsg), startsg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) startsg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #endif /* ASSERT_PDIR_SANITY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /**************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * I/O Pdir Resource Management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Bits set in the resource map are in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Each bit can represent a number of pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * LSbs represent lower addresses (IOVA's).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ***************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Convert from IOVP to IOVA and vice versa. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #ifdef ZX1_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* only support Astro and ancestors. Saves a few cycles in key places */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SBA_IOVP(ioc,iova) (iova)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned int bitshiftcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) + bitshiftcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * sba_search_bitmap - find free space in IO PDIR resource bitmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * @ioc: IO MMU structure which owns the pdir we are interested in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * @bits_wanted: number of entries we need.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Find consecutive free bits in resource bitmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Each bit represents one entry in the IO Pdir.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Cool perf optimization: search for log2(size) bits at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static SBA_INLINE unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) sba_search_bitmap(struct ioc *ioc, struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned long bits_wanted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned long *res_ptr = ioc->res_hint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned long pide = ~0UL, tpide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned long boundary_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned long shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) boundary_size = dma_get_seg_boundary_nr_pages(dev, IOVP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #if defined(ZX1_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) BUG_ON(ioc->ibase & ~IOVP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) shift = ioc->ibase >> IOVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (bits_wanted > (BITS_PER_LONG/2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Search word at a time - no mask needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) for(; res_ptr < res_end; ++res_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) tpide = ptr_to_pide(ioc, res_ptr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ret = iommu_is_span_boundary(tpide, bits_wanted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) boundary_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if ((*res_ptr == 0) && !ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *res_ptr = RESMAP_MASK(bits_wanted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pide = tpide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* point to the next word on next pass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) res_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ioc->res_bitshift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ** Search the resource bit map on well-aligned values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ** "o" is the alignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ** We need the alignment to invalidate I/O TLB using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ** SBA HW features in the unmap path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (bitshiftcnt >= BITS_PER_LONG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) bitshiftcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) res_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DBG_RES("%s() o %ld %p", __func__, o, res_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) while(res_ptr < res_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) WARN_ON(mask == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = iommu_is_span_boundary(tpide, bits_wanted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) boundary_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if ((((*res_ptr) & mask) == 0) && !ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) *res_ptr |= mask; /* mark resources busy! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pide = tpide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mask >>= o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) bitshiftcnt += o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (mask == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mask = RESMAP_MASK(bits_wanted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) bitshiftcnt=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) res_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* look in the same word on the next pass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ioc->res_bitshift = bitshiftcnt + bits_wanted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* wrapped ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (res_end <= res_ptr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ioc->res_hint = (unsigned long *) ioc->res_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ioc->res_bitshift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ioc->res_hint = res_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return (pide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * @ioc: IO MMU structure which owns the pdir we are interested in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * @size: number of bytes to create a mapping for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Given a size, find consecutive unmarked and then mark those bits in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * resource bit map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned int pages_needed = size >> IOVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned long cr_start = mfctl(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned long pide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pide = sba_search_bitmap(ioc, dev, pages_needed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (pide >= (ioc->res_size << 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) pide = sba_search_bitmap(ioc, dev, pages_needed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (pide >= (ioc->res_size << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) panic("%s: I/O MMU @ %p is out of mapping resources\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) __FILE__, ioc->ioc_hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #ifdef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* verify the first enable bit is clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __func__, size, pages_needed, pide,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ioc->res_bitshift );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned long cr_end = mfctl(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned long tmp = cr_end - cr_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* check for roll over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ioc->avg_search[ioc->avg_idx++] = cr_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ioc->used_pages += pages_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return (pide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * sba_free_range - unmark bits in IO PDIR resource bitmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * @ioc: IO MMU structure which owns the pdir we are interested in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * @iova: IO virtual address which was previously allocated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * @size: number of bytes to create a mapping for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * clear bits in the ioc's resource map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static SBA_INLINE void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned long iovp = SBA_IOVP(ioc, iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned int pide = PDIR_INDEX(iovp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned int ridx = pide >> 3; /* convert bit to byte address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int bits_not_wanted = size >> IOVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __func__, (uint) iova, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bits_not_wanted, m, pide, res_ptr, *res_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ioc->used_pages -= bits_not_wanted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) *res_ptr &= ~m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /**************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * "Dynamic DMA Mapping" support (aka "Coherent I/O")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ***************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #ifdef SBA_HINT_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) typedef unsigned long space_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define KERNEL_SPACE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * sba_io_pdir_entry - fill in one IO PDIR entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * @pdir_ptr: pointer to IO PDIR entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * @sid: process Space ID - currently only support KERNEL_SPACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * @vba: Virtual CPU address of buffer to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * @hint: DMA hint set to use for this mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * SBA Mapping Routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * Given a virtual address (vba, arg2) and space id, (sid, arg1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * pdir_ptr (arg0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * for Astro/Ike looks like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * 0 19 51 55 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * +-+---------------------+----------------------------------+----+--------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * |V| U | PPN[43:12] | U | VI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * +-+---------------------+----------------------------------+----+--------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * Pluto is basically identical, supports fewer physical address bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * 0 23 51 55 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * +-+------------------------+-------------------------------+----+--------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * |V| U | PPN[39:12] | U | VI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * +-+------------------------+-------------------------------+----+--------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * V == Valid Bit (Most Significant Bit is bit 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * U == Unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * PPN == Physical Page Number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * VI == Virtual Index (aka Coherent Index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * LPA instruction output is put into PPN field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * LCI (Load Coherence Index) instruction provides the "VI" bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * We pre-swap the bytes since PCX-W is Big Endian and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * IOMMU uses little endian for the pdir.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static void SBA_INLINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned long hint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u64 pa; /* physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) register unsigned ci; /* coherent index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pa = lpa(vba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) pa &= IOVP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) asm("lci 0(%1), %0" : "=r" (ci) : "r" (vba));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * (bit #61, big endian), we have to flush and sync every time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * IO-PDIR is changed in Ike/Astro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) asm_io_fdc(pdir_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * sba_mark_invalid - invalidate one or more IO PDIR entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * @ioc: IO MMU structure which owns the pdir we are interested in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * @iova: IO Virtual Address mapped earlier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * @byte_cnt: number of bytes this mapping covers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * Marking the IO PDIR entry(ies) as Invalid and invalidate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * is to purge stale entries in the IO TLB when unmapping entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * The PCOM register supports purging of multiple pages, with a minium
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * of 1 page and a maximum of 2GB. Hardware requires the address be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * aligned to the size of the range being purged. The size of the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * must be a power of 2. The "Cool perf optimization" in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * allocation routine helps keep that true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static SBA_INLINE void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 iovp = (u32) SBA_IOVP(ioc,iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #ifdef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Assert first pdir entry is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ** Even though this is a big-endian machine, the entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ** in the iopdir are little endian. That's why we look at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ** the byte at +7 instead of at +0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (0x80 != (((u8 *) pdir_ptr)[7])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (byte_cnt > IOVP_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned long entries_per_cacheline = ioc_needs_fdc ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) - (unsigned long) pdir_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) : 262144;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* set "size" field for PCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) iovp |= get_order(byte_cnt) + PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* clear I/O Pdir entry "valid" bit first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ((u8 *) pdir_ptr)[7] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) asm_io_fdc(pdir_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (ioc_needs_fdc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) entries_per_cacheline = L1_CACHE_SHIFT - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) pdir_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) byte_cnt -= IOVP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) } while (byte_cnt > IOVP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ** clear I/O PDIR entry "valid" bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ** We have to R/M/W the cacheline regardless how much of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ** pdir entry that we clobber.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ** The rest of the entry would be useful for debugging if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ** could dump core on HPMC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ((u8 *) pdir_ptr)[7] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) asm_io_fdc(pdir_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * sba_dma_supported - PCI driver can query DMA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * @dev: instance of PCI owned by the driver that's asking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * @mask: number of address bits this PCI device can handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * See Documentation/core-api/dma-api-howto.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int sba_dma_supported( struct device *dev, u64 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct ioc *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ioc = GET_IOC(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * check if mask is >= than the current max IO Virt Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * The max IO Virt address will *always* < 30 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return((int)(mask >= (ioc->ibase - 1 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * sba_map_single - map one buffer and return IOVA for DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * @dev: instance of PCI owned by the driver that's asking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * @addr: driver buffer to map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * @size: number of bytes to map in driver buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * @direction: R/W or both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * See Documentation/core-api/dma-api-howto.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static dma_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) sba_map_single(struct device *dev, void *addr, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) enum dma_data_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct ioc *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dma_addr_t iovp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dma_addr_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u64 *pdir_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int pide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ioc = GET_IOC(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (!ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return DMA_MAPPING_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* save offset bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* round up to nearest IOVP_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) spin_lock_irqsave(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #ifdef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) sba_check_pdir(ioc,"Check before sba_map_single()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ioc->msingle_calls++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ioc->msingle_pages += size >> IOVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pide = sba_alloc_range(ioc, dev, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) iovp = (dma_addr_t) pide << IOVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) DBG_RUN("%s() 0x%p -> 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) __func__, addr, (long) iovp | offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) pdir_start = &(ioc->pdir_base[pide]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) while (size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) pdir_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) (u8) (((u8 *) pdir_start)[7]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) (u8) (((u8 *) pdir_start)[6]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) (u8) (((u8 *) pdir_start)[5]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) (u8) (((u8 *) pdir_start)[4]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) (u8) (((u8 *) pdir_start)[3]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) (u8) (((u8 *) pdir_start)[2]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) (u8) (((u8 *) pdir_start)[1]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) (u8) (((u8 *) pdir_start)[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) addr += IOVP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) size -= IOVP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pdir_start++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) asm_io_sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #ifdef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) sba_check_pdir(ioc,"Check after sba_map_single()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) spin_unlock_irqrestore(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* form complete address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static dma_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) sba_map_page(struct device *dev, struct page *page, unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) size_t size, enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return sba_map_single(dev, page_address(page) + offset, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * sba_unmap_page - unmap one IOVA and free resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * @dev: instance of PCI owned by the driver that's asking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * @iova: IOVA of driver buffer previously mapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * @size: number of bytes mapped in driver buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * @direction: R/W or both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * See Documentation/core-api/dma-api-howto.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) enum dma_data_direction direction, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct ioc *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #if DELAYED_RESOURCE_CNT > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct sba_dma_pair *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dma_addr_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ioc = GET_IOC(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) WARN_ON(!ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) offset = iova & ~IOVP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) iova ^= offset; /* clear offset bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) size += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) size = ALIGN(size, IOVP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) spin_lock_irqsave(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ioc->usingle_calls++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ioc->usingle_pages += size >> IOVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) sba_mark_invalid(ioc, iova, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #if DELAYED_RESOURCE_CNT > 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Delaying when we re-use a IO Pdir entry reduces the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * of MMIO reads needed to flush writes to the PCOM register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) d = &(ioc->saved[ioc->saved_cnt]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) d->iova = iova;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) d->size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int cnt = ioc->saved_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) while (cnt--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) sba_free_range(ioc, d->iova, d->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) d--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ioc->saved_cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #else /* DELAYED_RESOURCE_CNT == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) sba_free_range(ioc, iova, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* If fdc's were issued, force fdc's to be visible now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) asm_io_sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #endif /* DELAYED_RESOURCE_CNT == 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) spin_unlock_irqrestore(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ** For Astro based systems this isn't a big deal WRT performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ** As long as 2.4 kernels copyin/copyout data from/to userspace,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ** we don't need the syncdma. The issue here is I/O MMU cachelines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ** are *not* coherent in all cases. May be hwrev dependent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ** Need to investigate more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) asm volatile("syncdma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * sba_alloc - allocate/map shared mem for DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * @hwdev: instance of PCI owned by the driver that's asking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * @size: number of bytes mapped in driver buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * @dma_handle: IOVA of new buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * See Documentation/core-api/dma-api-howto.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) gfp_t gfp, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) void *ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (!hwdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* only support PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) *dma_handle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret = (void *) __get_free_pages(gfp, get_order(size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) memset(ret, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) *dma_handle = sba_map_single(hwdev, ret, size, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * sba_free - free/unmap shared mem for DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * @hwdev: instance of PCI owned by the driver that's asking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * @size: number of bytes mapped in driver buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * @vaddr: virtual address IOVA of "consistent" buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * @dma_handler: IO virtual address of "consistent" buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * See Documentation/core-api/dma-api-howto.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) sba_free(struct device *hwdev, size_t size, void *vaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dma_addr_t dma_handle, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) sba_unmap_page(hwdev, dma_handle, size, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) free_pages((unsigned long) vaddr, get_order(size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ** Since 0 is a valid pdir_base index value, can't use that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ** to determine if a value is valid or not. Use a flag to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ** the SG list entry contains a valid pdir index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define PIDE_FLAG 0x80000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define IOMMU_MAP_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #include "iommu-helpers.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #ifdef DEBUG_LARGE_SG_ENTRIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int dump_run_sg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * sba_map_sg - map Scatter/Gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * @dev: instance of PCI owned by the driver that's asking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * @sglist: array of buffer/length pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * @nents: number of entries in list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * @direction: R/W or both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * See Documentation/core-api/dma-api-howto.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) enum dma_data_direction direction, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct ioc *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int coalesced, filled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ioc = GET_IOC(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (!ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Fast path single entry scatterlists. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (nents == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) sg_dma_address(sglist) = sba_map_single(dev, sg_virt(sglist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) sglist->length, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) sg_dma_len(sglist) = sglist->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) spin_lock_irqsave(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #ifdef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) sba_dump_sg(ioc, sglist, nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) panic("Check before sba_map_sg()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ioc->msg_calls++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ** First coalesce the chunks and allocate I/O pdir space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ** If this is one DMA stream, we can properly map using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ** correct virtual address associated with each DMA page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ** w/o this association, we wouldn't have coherent DMA!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ** Access to the virtual address is what forces a two pass algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) ** Program the I/O Pdir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ** map the virtual addresses to the I/O Pdir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ** o dma_address will contain the pdir index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ** o dma_len will contain the number of bytes to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ** o address contains the virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) asm_io_sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #ifdef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) sba_dump_sg(ioc, sglist, nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) panic("Check after sba_map_sg()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) spin_unlock_irqrestore(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * sba_unmap_sg - unmap Scatter/Gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * @dev: instance of PCI owned by the driver that's asking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * @sglist: array of buffer/length pairs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * @nents: number of entries in list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * @direction: R/W or both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * See Documentation/core-api/dma-api-howto.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) enum dma_data_direction direction, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct ioc *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #ifdef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) DBG_RUN_SG("%s() START %d entries, %p,%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) __func__, nents, sg_virt(sglist), sglist->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ioc = GET_IOC(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (!ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) WARN_ON(!ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ioc->usg_calls++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #ifdef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) spin_lock_irqsave(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) sba_check_pdir(ioc,"Check before sba_unmap_sg()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) spin_unlock_irqrestore(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) while (nents && sg_dma_len(sglist)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) sba_unmap_page(dev, sg_dma_address(sglist), sg_dma_len(sglist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) direction, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ioc->usingle_calls--; /* kluge since call is unmap_sg() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ++sglist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) nents--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #ifdef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) spin_lock_irqsave(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) sba_check_pdir(ioc,"Check after sba_unmap_sg()");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) spin_unlock_irqrestore(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static const struct dma_map_ops sba_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .dma_supported = sba_dma_supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .alloc = sba_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .free = sba_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .map_page = sba_map_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .unmap_page = sba_unmap_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .map_sg = sba_map_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .unmap_sg = sba_unmap_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .get_sgtable = dma_common_get_sgtable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .alloc_pages = dma_common_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .free_pages = dma_common_free_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ** SBA PAT PDC support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ** o call pdc_pat_cell_module()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ** o store ranges in PCI "resource" structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) sba_get_pat_resources(struct sba_device *sba_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ** TODO/REVISIT/FIXME: support for directed ranges requires calls to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ** PAT PDC to program the SBA/LBA directed range registers...this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ** burden may fall on the LBA code since it directly supports the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) ** PCI subsystem. It's not clear yet. - ggg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) FIXME : ???
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) Tells where the dvi bits are located in the address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) FIXME : ???
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /**************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * Initialization and claim
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ***************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) sba_alloc_pdir(unsigned int pdir_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) unsigned long pdir_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) unsigned long pdir_order = get_order(pdir_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (NULL == (void *) pdir_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) panic("%s() could not allocate I/O Page Table\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* If this is not PA8700 (PCX-W2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ** OR newer than ver 2.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ** OR in a system that doesn't need VINDEX bits from SBA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) ** then we aren't exposed to the HW bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) || (boot_cpu_data.pdc.versions > 0x202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) || (boot_cpu_data.pdc.capabilities & 0x08L) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return (void *) pdir_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * PA8700 (PCX-W2, aka piranha) silent data corruption fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * An interaction between PA8700 CPU (Ver 2.2 or older) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * Ike/Astro can cause silent data corruption. This is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * a problem if the I/O PDIR is located in memory such that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * (little-endian) bits 17 and 18 are on and bit 20 is off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * Since the max IO Pdir size is 2MB, by cleverly allocating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * right physical address, we can either avoid (IOPDIR <= 1MB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * or minimize (2MB IO Pdir) the problem if we restrict the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * IO Pdir to a maximum size of 2MB-128K (1902K).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * Because we always allocate 2^N sized IO pdirs, either of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * "bad" regions will be the last 128K if at all. That's easy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * to test for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (pdir_order <= (19-12)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* allocate a new one on 512k alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* release original */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) free_pages(pdir_base, pdir_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) pdir_base = new_pdir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* release excess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) while (pdir_order < (19-12)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) new_pdir += pdir_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) free_pages(new_pdir, pdir_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) pdir_order +=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) pdir_size <<=1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ** 1MB or 2MB Pdir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ** Needs to be aligned on an "odd" 1MB boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* release original */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) free_pages( pdir_base, pdir_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* release first 1MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) free_pages(new_pdir, 20-12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) pdir_base = new_pdir + 1024*1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (pdir_order > (20-12)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ** 2MB Pdir.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ** Flag tells init_bitmap() to mark bad 128k as used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ** and to reduce the size by 128k.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) piranha_bad_128k = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) new_pdir += 3*1024*1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) /* release last 1MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) free_pages(new_pdir, 20-12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* release unusable 128KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) free_pages(new_pdir - 128*1024 , 17-12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) pdir_size -= 128*1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) memset((void *) pdir_base, 0, pdir_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return (void *) pdir_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct ibase_data_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct ioc *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int ioc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static int setup_ibase_imask_callback(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) extern void lba_set_iregs(struct parisc_device *, u32, u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct parisc_device *lba = to_parisc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct ibase_data_struct *ibd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) int rope_num = (lba->hpa.start >> 13) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (rope_num >> 3 == ibd->ioc_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /* setup Mercury or Elroy IBASE/IMASK registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct ibase_data_struct ibase_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .ioc = ioc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .ioc_num = ioc_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) device_for_each_child(&sba->dev, &ibase_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) setup_ibase_imask_callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #ifdef SBA_AGP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) sba_ioc_find_quicksilver(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) int *agp_found = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) struct parisc_device *lba = to_parisc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (IS_QUICKSILVER(lba))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) *agp_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) u32 iova_space_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) u32 iova_space_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) int iov_order, tcnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #ifdef SBA_AGP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) int agp_found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ** Firmware programs the base and size of a "safe IOVA space"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ** (one that doesn't overlap memory or LMMIO space) in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ** IBASE and IMASK registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1fffffULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) iova_space_size /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ** iov_order is always based on a 1GB IOVA space since we want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ** turn on the other half for AGP GART.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) __func__, ioc->ioc_hpa, iova_space_size >> 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) iov_order + PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) get_order(ioc->pdir_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (!ioc->pdir_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) panic("Couldn't allocate I/O Page Table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) memset(ioc->pdir_base, 0, ioc->pdir_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) DBG_INIT("%s() pdir %p size %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) __func__, ioc->pdir_base, ioc->pdir_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #ifdef SBA_HINT_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) ioc->hint_shift_pdir, ioc->hint_mask_pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /* build IMASK for IOC and Elroy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) iova_space_mask = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) iova_space_mask <<= (iov_order + PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) ioc->imask = iova_space_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #ifdef ZX1_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) sba_dump_tlb(ioc->ioc_hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) setup_ibase_imask(sba, ioc, ioc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ** Setting the upper bits makes checking for bypass addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ** a little faster later on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ioc->imask |= 0xFFFFFFFF00000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* Set I/O PDIR Page size to system page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) switch (PAGE_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) case 12: tcnfg = 0; break; /* 4K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) case 13: tcnfg = 1; break; /* 8K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) case 14: tcnfg = 2; break; /* 16K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) case 16: tcnfg = 3; break; /* 64K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) panic(__FILE__ "Unsupported system page size %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) 1 << PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ** Program the IOC's ibase and enable IOVA translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) ** Bit zero == enable bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) ** Clear I/O TLB of any possible entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) ** (Yes. This is a bit paranoid...but so what)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #ifdef SBA_AGP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ** If an AGP device is present, only use half of the IOV space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ** for PCI DMA. Unfortunately we can't know ahead of time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ** whether GART support will actually be used, for now we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ** can just key on any AGP device found in the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ** We program the next pdir index after we stop w/ a key for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ** the GART code to handshake on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (agp_found && sba_reserve_agpgart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) __func__, (iova_space_size/2) >> 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) ioc->pdir_size /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #endif /*SBA_AGP_SUPPORT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) u32 iova_space_size, iova_space_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) unsigned int pdir_size, iov_order, tcnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ** Determine IOVA Space size from memory size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ** Ideally, PCI drivers would register the maximum number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ** of DMA they can have outstanding for each device they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ** own. Next best thing would be to guess how much DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) ** can be outstanding based on PCI Class/sub-class. Both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) ** methods still require some "extra" to support PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ** While we have 32-bits "IOVA" space, top two 2 bits are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ** for DMA hints - ergo only 30 bits max.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) iova_space_size = (u32) (totalram_pages()/global_ioc_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* limit IOVA space size to 1MB-1GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) iova_space_size = 1 << (20 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) iova_space_size = 1 << (30 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ** iova space must be log2() in size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) ** thus, pdir/res_map will also be log2().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) iov_order = get_order(iova_space_size << PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* iova_space_size is now bytes, not pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) iova_space_size = 1 << (iov_order + PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ioc->ioc_hpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) iova_space_size>>20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) iov_order + PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ioc->pdir_base = sba_alloc_pdir(pdir_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) DBG_INIT("%s() pdir %p size %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) __func__, ioc->pdir_base, pdir_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #ifdef SBA_HINT_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /* FIXME : DMA HINTs not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) ioc->hint_shift_pdir, ioc->hint_mask_pdir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* build IMASK for IOC and Elroy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) iova_space_mask = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) iova_space_mask <<= (iov_order + PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ** On C3000 w/512MB mem, HP-UX 10.20 reports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ** ibase=0, imask=0xFE000000, size=0x2000000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) ioc->ibase = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) ioc->imask = iova_space_mask; /* save it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #ifdef ZX1_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) __func__, ioc->ibase, ioc->imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ** FIXME: Hint registers are programmed with default hint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ** values during boot, so hints should be sane even if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) ** can't reprogram them the way drivers want.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) setup_ibase_imask(sba, ioc, ioc_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ** Program the IOC's ibase and enable IOVA translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /* Set I/O PDIR Page size to system page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) switch (PAGE_SHIFT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) case 12: tcnfg = 0; break; /* 4K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) case 13: tcnfg = 1; break; /* 8K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) case 14: tcnfg = 2; break; /* 16K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) case 16: tcnfg = 3; break; /* 64K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) panic(__FILE__ "Unsupported system page size %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) 1 << PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ** Clear I/O TLB of any possible entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ** (Yes. This is a bit paranoid...but so what)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) ioc->ibase = 0; /* used by SBA_IOVA and related macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) DBG_INIT("%s() DONE\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) ** SBA initialization code (HW and SW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) ** o identify SBA chip itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) ** o initialize SBA chip modes (HardFail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ** o initialize SBA chip modes (HardFail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) ** o FIXME: initialize DMA hints for reasonable defaults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return ioremap(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static void sba_hw_init(struct sba_device *sba_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) int num_ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) u64 ioc_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (!is_pdc_pat()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* Shutdown the USB controller on Astro-based workstations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ** Once we reprogram the IOMMU, the next DMA performed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) ** USB will HPMC the box. USB is only enabled if a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) ** keyboard is present and found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) ** With serial console, j6k v5.0 firmware says:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ** FIXME: Using GFX+USB console at power up but direct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) ** linux to serial console is still broken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ** USB could generate DMA so we must reset USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) ** The proper sequence would be:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ** o block console output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) ** o reset USB device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) ** o reprogram serial port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ** o unblock console output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) pdc_io_reset_devices();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ** Need to deal with DMA from LAN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ** Maybe use page zero boot device as a handle to talk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ** to PDC about which device to shutdown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ** Netbooting, j6k v5.0 firmware says:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ** ARGH! invalid class.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) pdc_io_reset();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (!IS_PLUTO(sba_dev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) __func__, sba_dev->sba_hpa, ioc_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* j6700 v1.6 firmware sets 0x294f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* A500 firmware sets 0x4d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #ifdef DEBUG_SBA_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) DBG_INIT(" 0x%Lx\n", ioc_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) } /* if !PLUTO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (IS_ASTRO(sba_dev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) num_ioc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) sba_dev->chip_resv.name = "Astro Intr Ack";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) BUG_ON(err < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) } else if (IS_PLUTO(sba_dev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) num_ioc = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) WARN_ON(err < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) sba_dev->iommu_resv.name = "IOVA Space";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) sba_dev->iommu_resv.start = 0x40000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) sba_dev->iommu_resv.end = 0x50000000UL - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) WARN_ON(err < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /* IKE, REO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) num_ioc = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /* TODO - LOOKUP Ike/Stretch chipset mem map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) /* XXX: What about Reo Grande? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) sba_dev->num_ioc = num_ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) for (i = 0; i < num_ioc; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) unsigned int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) * Clear ROPE(N)_CONFIG AO bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) * Disables "NT Ordering" (~= !"Relaxed Ordering")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) * Overrides bit 1 in DMA Hint Sets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) * Improves netperf UDP_STREAM by ~10% for bcm5701.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (IS_PLUTO(sba_dev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) void __iomem *rope_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) unsigned long cfg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) cfg_val = READ_REG(rope_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) cfg_val &= ~IOC_ROPE_AO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) WRITE_REG(cfg_val, rope_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) ** Make sure the box crashes on rope errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /* flush out the last writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (IS_PLUTO(sba_dev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) sba_common_init(struct sba_device *sba_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) /* add this one to the head of the list (order doesn't matter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ** This will be useful for debugging - especially if we get coredumps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) sba_dev->next = sba_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) sba_list = sba_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) for(i=0; i< sba_dev->num_ioc; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) int res_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) #ifdef DEBUG_DMB_TRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) extern void iterate_pages(unsigned long , unsigned long ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) void (*)(pte_t * , unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) unsigned long );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) void set_data_memory_break(pte_t * , unsigned long);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) /* resource map size dictated by pdir_size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) /* Second part of PIRANHA BUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (piranha_bad_128k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) res_size -= (128*1024)/sizeof(u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) res_size >>= 3; /* convert bit count to byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) DBG_INIT("%s() res_size 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) __func__, res_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) sba_dev->ioc[i].res_size = res_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #ifdef DEBUG_DMB_TRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) iterate_pages( sba_dev->ioc[i].res_map, res_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) set_data_memory_break, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (NULL == sba_dev->ioc[i].res_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) panic("%s:%s() could not allocate resource map\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) __FILE__, __func__ );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) memset(sba_dev->ioc[i].res_map, 0, res_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) /* next available IOVP - circular search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) sba_dev->ioc[i].res_hint = (unsigned long *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #ifdef ASSERT_PDIR_SANITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /* Mark first bit busy - ie no IOVA 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) sba_dev->ioc[i].res_map[0] = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /* Third (and last) part of PIRANHA BUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (piranha_bad_128k) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* region from +1408K to +1536 is un-usable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) int idx_start = (1408*1024/sizeof(u64)) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) int idx_end = (1536*1024/sizeof(u64)) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* mark that part of the io pdir busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) while (p_start < p_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) *p_start++ = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #ifdef DEBUG_DMB_TRAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) iterate_pages( sba_dev->ioc[i].res_map, res_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) set_data_memory_break, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) set_data_memory_break, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) DBG_INIT("%s() %d res_map %x %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) __func__, i, res_size, sba_dev->ioc[i].res_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) spin_lock_init(&sba_dev->sba_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #ifdef DEBUG_SBA_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * (bit #61, big endian), we have to flush and sync every time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * IO-PDIR is changed in Ike/Astro.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (ioc_needs_fdc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static int sba_proc_info(struct seq_file *m, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) struct sba_device *sba_dev = sba_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) unsigned long avg = 0, min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) seq_printf(m, "%s rev %d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) sba_dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) (sba_dev->hw_rev & 0x7) + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) (sba_dev->hw_rev & 0x18) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) (int)((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) total_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) for (i=0; i<4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #ifdef SBA_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) total_pages - ioc->used_pages, ioc->used_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) (int)(ioc->used_pages * 100 / total_pages));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) min = max = ioc->avg_search[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) avg += ioc->avg_search[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) avg /= SBA_SEARCH_SAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) min, avg, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) ioc->msingle_calls, ioc->msingle_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* KLUGE - unmap_sg calls unmap_single for each mapped page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) min = ioc->usingle_calls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) max = ioc->usingle_pages - ioc->usg_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) min, max, (int)((max * 1000)/min));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) ioc->msg_calls, ioc->msg_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) ioc->usg_calls, ioc->usg_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) sba_proc_bitmap_info(struct seq_file *m, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) struct sba_device *sba_dev = sba_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) ioc->res_size, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #endif /* CONFIG_PROC_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static const struct parisc_device_id sba_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static int sba_driver_callback(struct parisc_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static struct parisc_driver sba_driver __refdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .id_table = sba_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .probe = sba_driver_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ** Determine if sba should claim this chip (return 0) or not (return 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ** If so, initialize the chip and tell other partners in crime they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ** have work to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) static int __init sba_driver_callback(struct parisc_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) struct sba_device *sba_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) u32 func_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) char *version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) void __iomem *sba_addr = ioremap(dev->hpa.start, SBA_FUNC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) struct proc_dir_entry *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) sba_dump_ranges(sba_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) /* Read HW Rev First */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) func_class = READ_REG(sba_addr + SBA_FCLASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (IS_ASTRO(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) unsigned long fclass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static char astro_rev[]="Astro ?.?";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /* Astro is broken...Read HW Rev First */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) fclass = READ_REG(sba_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) astro_rev[6] = '1' + (char) (fclass & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) version = astro_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) } else if (IS_IKE(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static char ike_rev[] = "Ike rev ?";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) ike_rev[8] = '0' + (char) (func_class & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) version = ike_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) } else if (IS_PLUTO(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static char pluto_rev[]="Pluto ?.?";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) pluto_rev[8] = '0' + (char) (func_class & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) version = pluto_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static char reo_rev[] = "REO rev ?";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) reo_rev[8] = '0' + (char) (func_class & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) version = reo_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (!global_ioc_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) global_ioc_cnt = count_parisc_driver(&sba_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) /* Astro and Pluto have one IOC per SBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) global_ioc_cnt *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) printk(KERN_INFO "%s found %s at 0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) MODULE_NAME, version, (unsigned long long)dev->hpa.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (!sba_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) parisc_set_drvdata(dev, sba_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) for(i=0; i<MAX_IOC; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) spin_lock_init(&(sba_dev->ioc[i].res_lock));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) sba_dev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) sba_dev->hw_rev = func_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) sba_dev->name = dev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) sba_dev->sba_hpa = sba_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) sba_get_pat_resources(sba_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) sba_hw_init(sba_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) sba_common_init(sba_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) hppa_dma_ops = &sba_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) switch (dev->id.hversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) case PLUTO_MCKINLEY_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) root = proc_mckinley_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) case ASTRO_RUNWAY_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) case IKE_MERCED_PORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) root = proc_runway_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) proc_create_single("sba_iommu", 0, root, sba_proc_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) proc_create_single("sba_iommu-bitmap", 0, root, sba_proc_bitmap_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ** One time initialization to let the world know the SBA was found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) ** This is the only routine which is NOT static.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ** Must be called exactly once before pci_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) void __init sba_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) register_parisc_driver(&sba_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) * @dev: The parisc device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) * Returns the appropriate IOMMU data for the given parisc PCI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) * This is cached and used later for PCI DMA Mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) void * sba_get_iommu(struct parisc_device *pci_hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) struct parisc_device *sba_dev = parisc_parent(pci_hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) char t = sba_dev->id.hw_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) int iocnum = (pci_hba->hw_path >> 3); /* rope # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) return &(sba->ioc[iocnum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) * sba_directed_lmmio - return first directed LMMIO range routed to rope
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) * @pa_dev: The parisc device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * @r: resource PCI host controller wants start/end fields assigned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) * For the given parisc PCI controller, determine if any direct ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) * are routed down the corresponding rope.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) struct parisc_device *sba_dev = parisc_parent(pci_hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) char t = sba_dev->id.hw_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) r->start = r->end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) for (i=0; i<4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) int base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) void __iomem *reg = sba->sba_hpa + i*0x18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if ((base & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) continue; /* not enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if ((size & (ROPES_PER_IOC-1)) != rope)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) continue; /* directed down different rope */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) r->start = (base & ~1UL) | PCI_F_EXTEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) r->end = r->start + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) r->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) * sba_distributed_lmmio - return portion of distributed LMMIO range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) * @pa_dev: The parisc device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) * @r: resource PCI host controller wants start/end fields assigned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) * For the given parisc PCI controller, return portion of distributed LMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) * range. The distributed LMMIO is always present and it's just a question
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) * of the base address and size of the range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) struct parisc_device *sba_dev = parisc_parent(pci_hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) char t = sba_dev->id.hw_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) int base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) r->start = r->end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if ((base & 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) BUG(); /* Gah! Distr Range wasn't enabled! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) r->start = (base & ~1UL) | PCI_F_EXTEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) r->start += rope * (size + 1); /* adjust base for this rope */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) r->end = r->start + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) r->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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