^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) ** PCI Lower Bus Adapter (LBA) manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) ** (c) Copyright 1999,2000 Grant Grundler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) ** (c) Copyright 1999,2000 Hewlett-Packard Company
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ** This module primarily provides access to PCI bus (config/IOport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ** with 4 digit model numbers - eg C3000 (and A400...sigh).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ** LBA driver isn't as simple as the Dino driver because:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ** (a) this chip has substantial bug fixes between revisions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ** (Only one Dino bug has a software workaround :^( )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ** (b) has more options which we don't (yet) support (DMA hints, OLARD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ** (dino only deals with "Legacy" PDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ** (I/O SAPIC is integratd in the LBA chip).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ** FIXME: Add support for PCI card hot-plug (OLARD).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/init.h> /* for __init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/pdc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/pdcpat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/ropes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/hardware.h> /* for register_parisc_driver() stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/parisc-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/io.h> /* read/write stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "iommu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #undef DEBUG_LBA /* general stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #undef DEBUG_LBA_PORT /* debug I/O Port access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #undef FBB_SUPPORT /* Fast Back-Back xfers - NOT READY YET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #ifdef DEBUG_LBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DBG(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DBG(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #ifdef DEBUG_LBA_PORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DBG_PORT(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DBG_PORT(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifdef DEBUG_LBA_CFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DBG_CFG(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DBG_CFG(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #ifdef DEBUG_LBA_PAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DBG_PAT(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DBG_PAT(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ** Config accessor functions only pass in the 8-bit bus number and not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ** number based on what firmware wrote into the scratch register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ** The "secondary" bus number is set to this before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ** pci_register_ops(). If any PPB's are present, the scan will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ** discover them and update the "secondary" and "subordinate"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ** fields in the pci_bus structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ** Changes in the configuration *may* result in a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ** bus number for each LBA depending on what firmware does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MODULE_NAME "LBA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* non-postable I/O port space, densely packed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void __iomem *astro_iop_base __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static u32 lba_t32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* lba flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LBA_FLAG_SKIP_PROBE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline struct lba_device *LBA_DEV(struct pci_hba_data *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return container_of(hba, struct lba_device, hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ** Only allow 8 subsidiary busses per LBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ** Problem is the PCI bus numbering is globally shared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LBA_MAX_NUM_BUSES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * LBA register read and write support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * BE WARNED: register writes are posted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * (ie follow writes which must reach HW with a read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define READ_U8(addr) __raw_readb(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define READ_U16(addr) __raw_readw(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define READ_U32(addr) __raw_readl(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define WRITE_U8(value, addr) __raw_writeb(value, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define WRITE_U16(value, addr) __raw_writew(value, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define WRITE_U32(value, addr) __raw_writel(value, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define READ_REG8(addr) readb(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define READ_REG16(addr) readw(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define READ_REG32(addr) readl(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define READ_REG64(addr) readq(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define WRITE_REG8(value, addr) writeb(value, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define WRITE_REG16(value, addr) writew(value, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define WRITE_REG32(value, addr) writel(value, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ** Extract LBA (Rope) number from HPA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ** REVISIT: 16 ropes for Stretch/Ike?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ROPES_PER_IOC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LBA_NUM(x) ((((unsigned long) x) >> 13) & (ROPES_PER_IOC-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) lba_dump_res(struct resource *r, int d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (NULL == r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) printk(KERN_DEBUG "(%p)", r->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) for (i = d; i ; --i) printk(" ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) printk(KERN_DEBUG "%p [%lx,%lx]/%lx\n", r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) (long)r->start, (long)r->end, r->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) lba_dump_res(r->child, d+2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) lba_dump_res(r->sibling, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ** workaround for cfg cycles:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ** -- preserve LBA state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ** -- prevent any DMA from occurring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ** -- turn on smart mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ** -- probe with config writes before doing config reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ** -- check ERROR_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ** -- clear ERROR_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ** -- restore LBA state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ** The workaround is only used for device discovery.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int lba_device_present(u8 bus, u8 dfn, struct lba_device *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 first_bus = d->hba.hba_bus->busn_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 last_sub_bus = d->hba.hba_bus->busn_res.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if ((bus < first_bus) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) (bus > last_sub_bus) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ((bus - first_bus) >= LBA_MAX_NUM_BUSES)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define LBA_CFG_SETUP(d, tok) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Save contents of error config register. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Save contents of status control register. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ** arbitration for full bus walks. \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Save contents of arb mask register. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Turn off all device arbitration bits (i.e. everything \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * except arbitration enable bit). \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * Set the smart mode bit so that master aborts don't cause \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * LBA to go into PCI fatal mode (required). \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) WRITE_REG32(error_config | LBA_SMART_MODE, d->hba.base_addr + LBA_ERROR_CONFIG); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define LBA_CFG_PROBE(d, tok) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Setup Vendor ID write and read back the address register \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * to make sure that LBA is the bus master. \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * Read address register to ensure that LBA is the bus master, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * which implies that DMA traffic has stopped when DMA arb is off. \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * Generate a cfg write cycle (will have no affect on \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Vendor ID register since read-only). \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Make sure write has completed before proceeding further, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * i.e. before setting clear enable. \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * HPREVISIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * -- Can't tell if config cycle got the error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * OV bit is broken until rev 4.0, so can't use OV bit and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * As of rev 4.0, no longer need the error check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * -- Even if we could tell, we still want to return -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * for **ANY** error (not just master abort).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * -- Only clear non-fatal errors (we don't want to bring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * LBA out of pci-fatal mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * Actually, there is still a race in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * we could be clearing a fatal error. We will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * live with this during our initial bus walk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * until rev 4.0 (no driver activity during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * initial bus walk). The initial bus walk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * has race conditions concerning the use of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * smart mode as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define LBA_MASTER_ABORT_ERROR 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define LBA_FATAL_ERROR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 error_status = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Set clear enable (CE) bit. Unset by HW when new \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * errors are logged -- LBA HW ERS section 14.3.3). \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) WRITE_REG32(status_control | CLEAR_ERRLOG_ENABLE, base + LBA_STAT_CTL); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) error_status = READ_REG32(base + LBA_ERROR_STATUS); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if ((error_status & 0x1f) != 0) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Fail the config read request. \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) error = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if ((error_status & LBA_FATAL_ERROR) == 0) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Clear error status (if fatal bit not set) by setting \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * clear error log bit (CL). \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) WRITE_REG32(status_control | CLEAR_ERRLOG, base + LBA_STAT_CTL); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define LBA_CFG_ADDR_SETUP(d, addr) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Read address register to ensure that LBA is the bus master, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * which implies that DMA traffic has stopped when DMA arb is off. \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define LBA_CFG_RESTORE(d, base) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * Restore status control register (turn off clear enable). \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) WRITE_REG32(status_control, base + LBA_STAT_CTL); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Restore error config register (turn off smart mode). \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Restore arb mask register (reenables DMA arbitration). \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) lba_rd_cfg(struct lba_device *d, u32 tok, u8 reg, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 data = ~0U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 arb_mask = 0; /* used by LBA_CFG_SETUP/RESTORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 error_config = 0; /* used by LBA_CFG_SETUP/RESTORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 status_control = 0; /* used by LBA_CFG_SETUP/RESTORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) LBA_CFG_SETUP(d, tok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) LBA_CFG_PROBE(d, tok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) LBA_CFG_ADDR_SETUP(d, tok | reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case 1: data = (u32) READ_REG8(data_reg + (reg & 3)); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case 2: data = (u32) READ_REG16(data_reg+ (reg & 2)); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case 4: data = READ_REG32(data_reg); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) LBA_CFG_RESTORE(d, d->hba.base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int elroy_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 tok = LBA_CFG_TOK(local_bus, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if ((pos > 255) || (devfn > 255))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* FIXME: B2K/C3600 workaround is always use old method... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* if (!LBA_SKIP_PROBE(d)) */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* original - Generate config cycle on broken elroy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) with risk we will miss PCI bus errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *data = lba_rd_cfg(d, tok, pos, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DBG_CFG("%s(%x+%2x) -> 0x%x (a)\n", __func__, tok, pos, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (LBA_SKIP_PROBE(d) && !lba_device_present(bus->busn_res.start, devfn, d)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) DBG_CFG("%s(%x+%2x) -> -1 (b)\n", __func__, tok, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* either don't want to look or know device isn't present. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *data = ~0U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Basic Algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ** Should only get here on fully working LBA rev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ** This is how simple the code should have been.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) LBA_CFG_ADDR_SETUP(d, tok | pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) switch(size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case 1: *data = READ_REG8 (data_reg + (pos & 3)); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case 2: *data = READ_REG16(data_reg + (pos & 2)); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) case 4: *data = READ_REG32(data_reg); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DBG_CFG("%s(%x+%2x) -> 0x%x (c)\n", __func__, tok, pos, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) lba_wr_cfg(struct lba_device *d, u32 tok, u8 reg, u32 data, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 arb_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 error_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 status_control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) LBA_CFG_SETUP(d, tok);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) LBA_CFG_ADDR_SETUP(d, tok | reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case 1: WRITE_REG8 (data, data_reg + (reg & 3)); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case 2: WRITE_REG16(data, data_reg + (reg & 2)); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case 4: WRITE_REG32(data, data_reg); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) LBA_CFG_MASTER_ABORT_CHECK(d, d->hba.base_addr, tok, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) LBA_CFG_RESTORE(d, d->hba.base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * LBA 4.0 config write code implements non-postable semantics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * by doing a read of CONFIG ADDR after the write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int elroy_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 tok = LBA_CFG_TOK(local_bus,devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if ((pos > 255) || (devfn > 255))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!LBA_SKIP_PROBE(d)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Original Workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) lba_wr_cfg(d, tok, pos, (u32) data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) DBG_CFG("%s(%x+%2x) = 0x%x (a)\n", __func__, tok, pos,data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (LBA_SKIP_PROBE(d) && (!lba_device_present(bus->busn_res.start, devfn, d))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) DBG_CFG("%s(%x+%2x) = 0x%x (b)\n", __func__, tok, pos,data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 1; /* New Workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) DBG_CFG("%s(%x+%2x) = 0x%x (c)\n", __func__, tok, pos, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Basic Algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) LBA_CFG_ADDR_SETUP(d, tok | pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) switch(size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case 1: WRITE_REG8 (data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case 2: WRITE_REG16(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case 4: WRITE_REG32(data, d->hba.base_addr + LBA_PCI_CFG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static struct pci_ops elroy_cfg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .read = elroy_cfg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .write = elroy_cfg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * The mercury_cfg_ops are slightly misnamed; they're also used for Elroy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * TR4.0 as no additional bugs were found in this areea between Elroy and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Mercury
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int mercury_cfg_read(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 tok = LBA_CFG_TOK(local_bus, devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if ((pos > 255) || (devfn > 255))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) switch(size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) *data = READ_REG8(data_reg + (pos & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *data = READ_REG16(data_reg + (pos & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) *data = READ_REG32(data_reg); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DBG_CFG("mercury_cfg_read(%x+%2x) -> 0x%x\n", tok, pos, *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * LBA 4.0 config write code implements non-postable semantics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * by doing a read of CONFIG ADDR after the write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int mercury_cfg_write(struct pci_bus *bus, unsigned int devfn, int pos, int size, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct lba_device *d = LBA_DEV(parisc_walk_tree(bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) void __iomem *data_reg = d->hba.base_addr + LBA_PCI_CFG_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u32 tok = LBA_CFG_TOK(local_bus,devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if ((pos > 255) || (devfn > 255))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) DBG_CFG("%s(%x+%2x) <- 0x%x (c)\n", __func__, tok, pos, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) LBA_CFG_TR4_ADDR_SETUP(d, tok | pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) switch(size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) WRITE_REG8 (data, data_reg + (pos & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) WRITE_REG16(data, data_reg + (pos & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) WRITE_REG32(data, data_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* flush posted write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) lba_t32 = READ_U32(d->hba.base_addr + LBA_PCI_CFG_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static struct pci_ops mercury_cfg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .read = mercury_cfg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .write = mercury_cfg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) lba_bios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) DBG(MODULE_NAME ": lba_bios_init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * truncate_pat_collision: Deal with overlaps or outright collisions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * between PAT PDC reported ranges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * Broken PA8800 firmware will report lmmio range that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * overlaps with CPU HPA. Just truncate the lmmio range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * BEWARE: conflicts with this lmmio range may be an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * elmmio range which is pointing down another rope.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * FIXME: only deals with one collision per range...theoretically we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * could have several. Supporting more than one collision will get messy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) truncate_pat_collision(struct resource *root, struct resource *new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned long start = new->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned long end = new->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct resource *tmp = root->child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (end <= start || start < root->start || !tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* find first overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) while (tmp && tmp->end < start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) tmp = tmp->sibling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* no entries overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (!tmp) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* found one that starts behind the new one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ** Don't need to do anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (tmp->start >= end) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (tmp->start <= start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* "front" of new one overlaps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) new->start = tmp->end + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (tmp->end >= end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* AACCKK! totally overlaps! drop this range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (tmp->end < end ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* "end" of new one overlaps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) new->end = tmp->start - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) printk(KERN_WARNING "LBA: Truncating lmmio_space [%lx/%lx] "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "to [%lx,%lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) start, end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) (long)new->start, (long)new->end );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0; /* truncation successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * extend_lmmio_len: extend lmmio range to maximum length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * This is needed at least on C8000 systems to get the ATI FireGL card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * working. On other systems we will currently not extend the lmmio space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) extend_lmmio_len(unsigned long start, unsigned long end, unsigned long lba_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct resource *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* exit if not a C8000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (boot_cpu_data.cpu_type < mako)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pr_debug("LMMIO mismatch: PAT length = 0x%lx, MASK register = 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) end - start, lba_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) lba_len = min(lba_len+1, 256UL*1024*1024); /* limit to 256 MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - original\n", start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) end += lba_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (end < start) /* fix overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) end = -1ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pr_debug("LBA: lmmio_space [0x%lx-0x%lx] - current\n", start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* first overlap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pr_debug("LBA: testing %pR\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (tmp->start == start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) continue; /* ignore ourself */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (tmp->end < start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (tmp->start > end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (end >= tmp->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) end = tmp->start - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) pr_info("LBA: lmmio_space [0x%lx-0x%lx] - new\n", start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* return new end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define truncate_pat_collision(r,n) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static void pcibios_allocate_bridge_resources(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) r = &dev->resource[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) if (!r->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (r->parent) /* Already allocated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!r->start || pci_claim_bridge_resource(dev, idx) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * Something is wrong with the region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * Invalidate the resource to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * child resource allocations in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) r->start = r->end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) r->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static void pcibios_allocate_bus_resources(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct pci_bus *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* Depth-First Search on bus tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (bus->self)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) pcibios_allocate_bridge_resources(bus->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) list_for_each_entry(child, &bus->children, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) pcibios_allocate_bus_resources(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ** The algorithm is generic code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ** But it needs to access local data structures to get the IRQ base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ** Could make this a "pci_fixup_irq(bus, region)" but not sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ** it's worth it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ** Resources aren't allocated until recursive buswalk below HBA is completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) lba_fixup_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #ifdef FBB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct lba_device *ldev = LBA_DEV(parisc_walk_tree(bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) DBG("lba_fixup_bus(0x%p) bus %d platform_data 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) bus, (int)bus->busn_res.start, bus->bridge->platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ** Properly Setup MMIO resources for this bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ** pci_alloc_primary_bus() mangles this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (bus->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* PCI-PCI Bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) pci_read_bridge_bases(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* check and allocate bridge resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pcibios_allocate_bus_resources(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Host-PCI Bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ldev->hba.io_space.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ldev->hba.io_space.start, ldev->hba.io_space.end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ldev->hba.io_space.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) DBG("lba_fixup_bus() %s [%lx/%lx]/%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ldev->hba.lmmio_space.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ldev->hba.lmmio_space.start, ldev->hba.lmmio_space.end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ldev->hba.lmmio_space.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) err = request_resource(&ioport_resource, &(ldev->hba.io_space));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) lba_dump_res(&ioport_resource, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (ldev->hba.elmmio_space.flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) err = request_resource(&iomem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) &(ldev->hba.elmmio_space));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) printk("FAILED: lba_fixup_bus() request for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "elmmio_space [%lx/%lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) (long)ldev->hba.elmmio_space.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (long)ldev->hba.elmmio_space.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* lba_dump_res(&iomem_resource, 2); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* BUG(); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (ldev->hba.lmmio_space.flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) err = request_resource(&iomem_resource, &(ldev->hba.lmmio_space));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) printk(KERN_ERR "FAILED: lba_fixup_bus() request for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "lmmio_space [%lx/%lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) (long)ldev->hba.lmmio_space.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) (long)ldev->hba.lmmio_space.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* GMMIO is distributed range. Every LBA/Rope gets part it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (ldev->hba.gmmio_space.flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) err = request_resource(&iomem_resource, &(ldev->hba.gmmio_space));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) printk("FAILED: lba_fixup_bus() request for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) "gmmio_space [%lx/%lx]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) (long)ldev->hba.gmmio_space.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) (long)ldev->hba.gmmio_space.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) lba_dump_res(&iomem_resource, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) DBG("lba_fixup_bus() %s\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* Virtualize Device/Bridge Resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct resource *res = &dev->resource[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* If resource not allocated - skip it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!res->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ** FIXME: this will result in whinging for devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ** that share expansion ROMs (think quad tulip), but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ** isn't harmful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) pci_claim_resource(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #ifdef FBB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ** If one device does not support FBB transfers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ** No one on the bus can be allowed to use them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) (void) pci_read_config_word(dev, PCI_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) bus->bridge_ctl &= ~(status & PCI_STATUS_FAST_BACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ** P2PB's have no IRQs. ignore them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) pcibios_init_bridge(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* Adjust INTERRUPT_LINE for this dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) iosapic_fixup_irq(ldev->iosapic_obj, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #ifdef FBB_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* FIXME/REVISIT - finish figuring out to set FBB on both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ** pci_setup_bridge() clobbers PCI_BRIDGE_CONTROL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ** Can't fixup here anyway....garr...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (fbb_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (bus->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u8 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* enable on PPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) (void) pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, control | PCI_STATUS_FAST_BACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* enable on LBA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) fbb_enable = PCI_COMMAND_FAST_BACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Lastly enable FBB/PERR/SERR on all devices too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) (void) pci_read_config_word(dev, PCI_COMMAND, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) status |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR | fbb_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) (void) pci_write_config_word(dev, PCI_COMMAND, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static struct pci_bios_ops lba_bios_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .init = lba_bios_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .fixup_bus = lba_fixup_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /*******************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ** LBA Sprockets "I/O Port" Space Accessor Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ** This set of accessor functions is intended for use with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ** Many PCI devices don't require use of I/O port space (eg Tulip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ** NCR720) since they export the same registers to both MMIO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ** I/O port space. In general I/O port space is slower than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ** MMIO since drivers are designed so PIO writes can be posted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ********************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define LBA_PORT_IN(size, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u##size t; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) t = READ_REG##size(astro_iop_base + addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) DBG_PORT(" 0x%x\n", t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return (t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) LBA_PORT_IN( 8, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) LBA_PORT_IN(16, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) LBA_PORT_IN(32, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ** guarantee non-postable completion semantics - not avoid X4107.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ** The READ_U32 only guarantees the write data gets to elroy but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ** out to the PCI bus. We can't read stuff from I/O port space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ** since we don't know what has side-effects. Attempting to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ** from configuration space would be suicidal given the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ** bugs in that elroy functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ** Description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ** DMA read results can improperly pass PIO writes (X4107). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ** result of this bug is that if a processor modifies a location in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ** memory after having issued PIO writes, the PIO writes are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ** guaranteed to be completed before a PCI device is allowed to see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ** the modified data in a DMA read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ** Note that IKE bug X3719 in TR1 IKEs will result in the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ** symptom.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ** Workaround:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ** The workaround for this bug is to always follow a PIO write with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ** a PIO read to the same bus before starting DMA on that PCI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define LBA_PORT_OUT(size, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, d, addr, val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) WRITE_REG##size(val, astro_iop_base + addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (LBA_DEV(d)->hw_rev < 3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) LBA_PORT_OUT( 8, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) LBA_PORT_OUT(16, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) LBA_PORT_OUT(32, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static struct pci_port_ops lba_astro_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .inb = lba_astro_in8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .inw = lba_astro_in16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .inl = lba_astro_in32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .outb = lba_astro_out8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .outw = lba_astro_out16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .outl = lba_astro_out32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define PIOP_TO_GMMIO(lba, addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /*******************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ** LBA PAT "I/O Port" Space Accessor Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ** This set of accessor functions is intended for use with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ** This uses the PIOP space located in the first 64MB of GMMIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ** bits 1:0 stay the same. bits 15:2 become 25:12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ** Then add the base and we can generate an I/O Port cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ********************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #undef LBA_PORT_IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define LBA_PORT_IN(size, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) u##size t; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) DBG_PORT("%s(0x%p, 0x%x) ->", __func__, l, addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) DBG_PORT(" 0x%x\n", t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return (t); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) LBA_PORT_IN( 8, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) LBA_PORT_IN(16, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) LBA_PORT_IN(32, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #undef LBA_PORT_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define LBA_PORT_OUT(size, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) void __iomem *where = PIOP_TO_GMMIO(LBA_DEV(l), addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) DBG_PORT("%s(0x%p, 0x%x, 0x%x)\n", __func__, l, addr, val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) WRITE_REG##size(val, where); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* flush the I/O down to the elroy at least */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) LBA_PORT_OUT( 8, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) LBA_PORT_OUT(16, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) LBA_PORT_OUT(32, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static struct pci_port_ops lba_pat_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .inb = lba_pat_in8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .inw = lba_pat_in16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .inl = lba_pat_in32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .outb = lba_pat_out8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .outw = lba_pat_out16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .outl = lba_pat_out32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ** make range information from PDC available to PCI subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ** We make the PDC call here in order to get the PCI bus range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ** numbers. The rest will get forwarded in pcibios_fixup_bus().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ** We don't have a struct pci_bus assigned to us yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) unsigned long bytecnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) long io_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) long status; /* PDC return status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) long pa_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) pdc_pat_cell_mod_maddr_block_t *pa_pdc_cell; /* PA_VIEW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) pdc_pat_cell_mod_maddr_block_t *io_pdc_cell; /* IO_VIEW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) pa_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (!pa_pdc_cell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) io_pdc_cell = kzalloc(sizeof(pdc_pat_cell_mod_maddr_block_t), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (!io_pdc_cell) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) kfree(pa_pdc_cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /* return cell module (IO view) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) status = pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PA_VIEW, pa_pdc_cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) pa_count = pa_pdc_cell->mod[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) status |= pdc_pat_cell_module(&bytecnt, pa_dev->pcell_loc, pa_dev->mod_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) IO_VIEW, io_pdc_cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) io_count = io_pdc_cell->mod[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* We've already done this once for device discovery...*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (status != PDC_OK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) panic("pdc_pat_cell_module() call failed for LBA!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (PAT_GET_ENTITY(pa_pdc_cell->mod_info) != PAT_ENTITY_LBA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ** Inspect the resources PAT tells us about
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) for (i = 0; i < pa_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) unsigned long type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) unsigned long start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) unsigned long end; /* aka finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) } *p, *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) p = (void *) &(pa_pdc_cell->mod[2+i*3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) io = (void *) &(io_pdc_cell->mod[2+i*3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* Convert the PAT range data to PCI "struct resource" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) switch(p->type & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) case PAT_PBNUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) lba_dev->hba.bus_num.start = p->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) lba_dev->hba.bus_num.end = p->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) lba_dev->hba.bus_num.flags = IORESOURCE_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case PAT_LMMIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* used to fix up pre-initialized MEM BARs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!lba_dev->hba.lmmio_space.flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) unsigned long lba_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) lba_len = ~READ_REG32(lba_dev->hba.base_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) + LBA_LMMIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if ((p->end - p->start) != lba_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) p->end = extend_lmmio_len(p->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) p->end, lba_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) sprintf(lba_dev->hba.lmmio_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "PCI%02x LMMIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) (int)lba_dev->hba.bus_num.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) lba_dev->hba.lmmio_space_offset = p->start -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) io->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) r = &lba_dev->hba.lmmio_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) r->name = lba_dev->hba.lmmio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) } else if (!lba_dev->hba.elmmio_space.flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) sprintf(lba_dev->hba.elmmio_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) "PCI%02x ELMMIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) (int)lba_dev->hba.bus_num.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) r = &lba_dev->hba.elmmio_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) r->name = lba_dev->hba.elmmio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) printk(KERN_WARNING MODULE_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) " only supports 2 LMMIO resources!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) r->start = p->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) r->end = p->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) r->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) r->parent = r->sibling = r->child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) case PAT_GMMIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /* MMIO space > 4GB phys addr; for 64-bit BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) sprintf(lba_dev->hba.gmmio_name, "PCI%02x GMMIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) (int)lba_dev->hba.bus_num.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) r = &lba_dev->hba.gmmio_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) r->name = lba_dev->hba.gmmio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) r->start = p->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) r->end = p->end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) r->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) r->parent = r->sibling = r->child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) case PAT_NPIOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) printk(KERN_WARNING MODULE_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) " range[%d] : ignoring NPIOP (0x%lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) i, p->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) case PAT_PIOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ** Postable I/O port space is per PCI host adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ** base of 64MB PIOP region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) lba_dev->iop_base = ioremap(p->start, 64 * 1024 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) (int)lba_dev->hba.bus_num.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) r = &lba_dev->hba.io_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) r->name = lba_dev->hba.io_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) r->start = HBA_PORT_BASE(lba_dev->hba.hba_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) r->end = r->start + HBA_PORT_SPACE_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) r->flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) r->parent = r->sibling = r->child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) printk(KERN_WARNING MODULE_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) " range[%d] : unknown pat range type (0x%lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) i, p->type & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) kfree(pa_pdc_cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) kfree(io_pdc_cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* keep compiler from complaining about missing declarations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define lba_pat_port_ops lba_astro_port_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define lba_pat_resources(pa_dev, lba_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #endif /* CONFIG_64BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) extern void sba_distributed_lmmio(struct parisc_device *, struct resource *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) extern void sba_directed_lmmio(struct parisc_device *, struct resource *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int lba_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) lba_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ** With "legacy" firmware, the lowest byte of FW_SCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ** represents bus->secondary and the second byte represents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ** bus->subsidiary (i.e. highest PPB programmed by firmware).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ** PCI bus walk *should* end up with the same result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ** FIXME: But we don't have sanity checks in PCI or LBA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) lba_num = READ_REG32(lba_dev->hba.base_addr + LBA_FW_SCRATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) r = &(lba_dev->hba.bus_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) r->name = "LBA PCI Busses";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) r->start = lba_num & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) r->end = (lba_num>>8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) r->flags = IORESOURCE_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* Set up local PCI Bus resources - we don't need them for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ** Legacy boxes but it's nice to see in /proc/iomem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) r = &(lba_dev->hba.lmmio_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) sprintf(lba_dev->hba.lmmio_name, "PCI%02x LMMIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) (int)lba_dev->hba.bus_num.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) r->name = lba_dev->hba.lmmio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /* We want the CPU -> IO routing of addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * The SBA BASE/MASK registers control CPU -> IO routing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * Ask SBA what is routed to this rope/LBA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) sba_distributed_lmmio(pa_dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * The LBA BASE/MASK registers control IO -> System routing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * The following code works but doesn't get us what we want.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * Well, only because firmware (v5.0) on C3000 doesn't program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * the LBA BASE/MASE registers to be the exact inverse of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * the corresponding SBA registers. Other Astro/Pluto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * based platform firmware may do it right.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * Should someone want to mess with MSI, they may need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * reprogram LBA BASE/MASK registers. Thus preserve the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * below until MSI is known to work on C3000/A500/N4000/RP3440.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * Using the code below, /proc/iomem shows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * f0000000-f0ffffff : PCI00 LMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) * f05d0000-f05d0000 : lcd_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * f05d0008-f05d0008 : lcd_cmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * f1000000-f1ffffff : PCI01 LMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * f4000000-f4ffffff : PCI02 LMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) * f4000000-f4001fff : sym53c8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) * f4002000-f4003fff : sym53c8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) * f4004000-f40043ff : sym53c8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * f4005000-f40053ff : sym53c8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * f4007000-f4007fff : ohci_hcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * f4008000-f40083ff : tulip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * f6000000-f6ffffff : PCI03 LMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * f8000000-fbffffff : PCI00 ELMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * fa100000-fa4fffff : stifb mmio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * fb000000-fb1fffff : stifb fb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * But everything listed under PCI02 actually lives under PCI00.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * This is clearly wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * Asking SBA how things are routed tells the correct story:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * LMMIO_BASE/MASK/ROUTE f4000001 fc000000 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * DIR0_BASE/MASK/ROUTE fa000001 fe000000 00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * DIR1_BASE/MASK/ROUTE f9000001 ff000000 00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * DIR2_BASE/MASK/ROUTE f0000000 fc000000 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * DIR3_BASE/MASK/ROUTE f0000000 fc000000 00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * Which looks like this in /proc/iomem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * f4000000-f47fffff : PCI00 LMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * f4000000-f4001fff : sym53c8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * ...[deteled core devices - same as above]...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * f4008000-f40083ff : tulip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * f4800000-f4ffffff : PCI01 LMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * f6000000-f67fffff : PCI02 LMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * f7000000-f77fffff : PCI03 LMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * f9000000-f9ffffff : PCI02 ELMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) * fa000000-fbffffff : PCI03 ELMMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) * fa100000-fa4fffff : stifb mmio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * fb000000-fb1fffff : stifb fb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * ie all Built-in core are under now correctly under PCI00.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * The "PCI02 ELMMIO" directed range is for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * +-[02]---03.0 3Dfx Interactive, Inc. Voodoo 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * All is well now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) r->start = READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (r->start & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) unsigned long rsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) r->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* mmio_mask also clears Enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) r->start &= mmio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) rsize = ~ READ_REG32(lba_dev->hba.base_addr + LBA_LMMIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ** Each rope only gets part of the distributed range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ** Adjust "window" for this rope.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) rsize /= ROPES_PER_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) r->start += (rsize + 1) * LBA_NUM(pa_dev->hpa.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) r->end = r->start + rsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) r->end = r->start = 0; /* Not enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ** "Directed" ranges are used when the "distributed range" isn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ** sufficient for all devices below a given LBA. Typically devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ** like graphics cards or X25 may need a directed range when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ** bus has multiple slots (ie multiple devices) or the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ** needs more than the typical 4 or 8MB a distributed range offers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ** The main reason for ignoring it now frigging complications.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) ** Directed ranges may overlap (and have precedence) over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ** distributed ranges. Or a distributed range assigned to a unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ** rope may be used by a directed range on a different rope.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ** Support for graphics devices may require fixing this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ** since they may be assigned a directed range which overlaps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ** an existing (but unused portion of) distributed range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) r = &(lba_dev->hba.elmmio_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) sprintf(lba_dev->hba.elmmio_name, "PCI%02x ELMMIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) (int)lba_dev->hba.bus_num.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) r->name = lba_dev->hba.elmmio_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /* See comment which precedes call to sba_directed_lmmio() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) sba_directed_lmmio(pa_dev, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) r->start = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (r->start & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) unsigned long rsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) r->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* mmio_mask also clears Enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) r->start &= mmio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) r->start = PCI_HOST_ADDR(&lba_dev->hba, r->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) rsize = READ_REG32(lba_dev->hba.base_addr + LBA_ELMMIO_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) r->end = r->start + ~rsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) r = &(lba_dev->hba.io_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) sprintf(lba_dev->hba.io_name, "PCI%02x Ports",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) (int)lba_dev->hba.bus_num.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) r->name = lba_dev->hba.io_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) r->flags = IORESOURCE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) r->start = READ_REG32(lba_dev->hba.base_addr + LBA_IOS_BASE) & ~1L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) r->end = r->start + (READ_REG32(lba_dev->hba.base_addr + LBA_IOS_MASK) ^ (HBA_PORT_SPACE_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) /* Virtualize the I/O Port space ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) lba_num = HBA_PORT_BASE(lba_dev->hba.hba_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) r->start |= lba_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) r->end |= lba_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /**************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) ** LBA initialization code (HW and SW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ** o identify LBA chip itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ** o initialize LBA chip modes (HardFail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ** o FIXME: initialize DMA hints for reasonable defaults
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ** o enable configuration functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) **************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) lba_hw_init(struct lba_device *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) u32 bus_reset; /* PDC_PAT_BUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) printk(KERN_DEBUG "LBA %lx STAT_CTL %Lx ERROR_CFG %Lx STATUS %Lx DMA_CTL %Lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) d->hba.base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) READ_REG64(d->hba.base_addr + LBA_STAT_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) READ_REG64(d->hba.base_addr + LBA_ERROR_CONFIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) READ_REG64(d->hba.base_addr + LBA_ERROR_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) READ_REG64(d->hba.base_addr + LBA_DMA_CTL) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) printk(KERN_DEBUG " ARB mask %Lx pri %Lx mode %Lx mtlt %Lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) READ_REG64(d->hba.base_addr + LBA_ARB_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) READ_REG64(d->hba.base_addr + LBA_ARB_PRI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) READ_REG64(d->hba.base_addr + LBA_ARB_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) READ_REG64(d->hba.base_addr + LBA_ARB_MTLT) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) printk(KERN_DEBUG " HINT cfg 0x%Lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) READ_REG64(d->hba.base_addr + LBA_HINT_CFG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) printk(KERN_DEBUG " HINT reg ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) { int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) for (i=LBA_HINT_BASE; i< (14*8 + LBA_HINT_BASE); i+=8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) printk(" %Lx", READ_REG64(d->hba.base_addr + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #endif /* DEBUG_LBA_PAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #ifdef CONFIG_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) * FIXME add support for PDC_PAT_IO "Get slot status" - OLAR support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * Only N-Class and up can really make use of Get slot status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * maybe L-class too but I've never played with it there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /* PDC_PAT_BUG: exhibited in rev 40.48 on L2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) bus_reset = READ_REG32(d->hba.base_addr + LBA_STAT_CTL + 4) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (bus_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) printk(KERN_DEBUG "NOTICE: PCI bus reset still asserted! (clearing)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) stat = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (stat & LBA_SMART_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) printk(KERN_DEBUG "NOTICE: LBA in SMART mode! (cleared)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) stat &= ~LBA_SMART_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) WRITE_REG32(stat, d->hba.base_addr + LBA_ERROR_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * Hard Fail vs. Soft Fail on PCI "Master Abort".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) * "Master Abort" means the MMIO transaction timed out - usually due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) * the device not responding to an MMIO read. We would like HF to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * enabled to find driver problems, though it means the system will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * crash with a HPMC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * In SoftFail mode "~0L" is returned as a result of a timeout on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * pci bus. This is like how PCI busses on x86 and most other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * architectures behave. In order to increase compatibility with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * existing (x86) PCI hardware and existing Linux drivers we enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * Soft Faul mode on PA-RISC now too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) stat = READ_REG32(d->hba.base_addr + LBA_STAT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #if defined(ENABLE_HARDFAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) WRITE_REG32(stat | HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) WRITE_REG32(stat & ~HF_ENABLE, d->hba.base_addr + LBA_STAT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ** Writing a zero to STAT_CTL.rf (bit 0) will clear reset signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ** if it's not already set. If we just cleared the PCI Bus Reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ** signal, wait a bit for the PCI devices to recover and setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (bus_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) mdelay(pci_post_reset_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (0 == READ_REG32(d->hba.base_addr + LBA_ARB_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ** PDC_PAT_BUG: PDC rev 40.48 on L2000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) ** B2000/C3600/J6000 also have this problem?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) ** Elroys with hot pluggable slots don't get configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ** correctly if the slot is empty. ARB_MASK is set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) ** and we can't master transactions on the bus if it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ** not at least one. 0x3 enables elroy and first slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) printk(KERN_DEBUG "NOTICE: Enabling PCI Arbitration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) WRITE_REG32(0x3, d->hba.base_addr + LBA_ARB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ** FIXME: Hint registers are programmed with default hint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ** values by firmware. Hints should be sane even if we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ** can't reprogram them the way drivers want.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) * Unfortunately, when firmware numbers busses, it doesn't take into account
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * Cardbus bridges. So we have to renumber the busses to suit ourselves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * Elroy/Mercury don't actually know what bus number they're attached to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) * we use bus 0 to indicate the directly attached bus and any other bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) * number will be taken care of by the PCI-PCI bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static unsigned int lba_next_bus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) * Determine if lba should claim this chip (return 0) or not (return 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) * If so, initialize the chip and tell other partners in crime they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) * have work to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) lba_driver_probe(struct parisc_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct lba_device *lba_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) LIST_HEAD(resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct pci_bus *lba_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct pci_ops *cfg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) u32 func_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) void *tmp_obj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) char *version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) void __iomem *addr = ioremap(dev->hpa.start, 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) int max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /* Read HW Rev First */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) func_class = READ_REG32(addr + LBA_FCLASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (IS_ELROY(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) func_class &= 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) switch (func_class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) case 0: version = "TR1.0"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) case 1: version = "TR2.0"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) case 2: version = "TR2.1"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) case 3: version = "TR2.2"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) case 4: version = "TR3.0"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) case 5: version = "TR4.0"; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) default: version = "TR4+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) printk(KERN_INFO "Elroy version %s (0x%x) found at 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) version, func_class & 0xf, (long)dev->hpa.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (func_class < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) printk(KERN_WARNING "Can't support LBA older than "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) "TR2.1 - continuing under adversity.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* Elroy TR4.0 should work with simple algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) But it doesn't. Still missing something. *sigh*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (func_class > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) cfg_ops = &mercury_cfg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) cfg_ops = &elroy_cfg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) } else if (IS_MERCURY(dev) || IS_QUICKSILVER(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) int major, minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) func_class &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) major = func_class >> 4, minor = func_class & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /* We could use one printk for both Elroy and Mercury,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * but for the mask for func_class.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) printk(KERN_INFO "%s version TR%d.%d (0x%x) found at 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) IS_MERCURY(dev) ? "Mercury" : "Quicksilver", major,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) minor, func_class, (long)dev->hpa.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) cfg_ops = &mercury_cfg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) printk(KERN_ERR "Unknown LBA found at 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) (long)dev->hpa.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* Tell I/O SAPIC driver we have a IRQ handler/region. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) tmp_obj = iosapic_register(dev->hpa.start + LBA_IOSAPIC_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /* NOTE: PCI devices (e.g. 103c:1005 graphics card) which don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ** have an IRT entry will get NULL back from iosapic code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) lba_dev = kzalloc(sizeof(struct lba_device), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (!lba_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) printk(KERN_ERR "lba_init_chip - couldn't alloc lba_device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) return(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* ---------- First : initialize data we already have --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) lba_dev->hw_rev = func_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) lba_dev->hba.base_addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) lba_dev->hba.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) lba_dev->iosapic_obj = tmp_obj; /* save interrupt handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) lba_dev->hba.iommu = sba_get_iommu(dev); /* get iommu data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) parisc_set_drvdata(dev, lba_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) /* ------------ Second : initialize common stuff ---------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) pci_bios = &lba_bios_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) pcibios_register_hba(&lba_dev->hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) spin_lock_init(&lba_dev->lba_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) if (lba_hw_init(lba_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) return(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /* ---------- Third : setup I/O Port and MMIO resources --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (is_pdc_pat()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* PDC PAT firmware uses PIOP region of GMMIO space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) pci_port = &lba_pat_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* Go ask PDC PAT what resources this LBA has */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) lba_pat_resources(dev, lba_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (!astro_iop_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) /* Sprockets PDC uses NPIOP region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) astro_iop_base = ioremap(LBA_PORT_BASE, 64 * 1024);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) pci_port = &lba_astro_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) /* Poke the chip a bit for /proc output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) lba_legacy_resources(dev, lba_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (lba_dev->hba.bus_num.start < lba_next_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) lba_dev->hba.bus_num.start = lba_next_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* Overlaps with elmmio can (and should) fail here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) * We will prune (or ignore) the distributed range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * FIXME: SBA code should register all elmmio ranges first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) * that would take care of elmmio ranges routed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) * to a different rope (already discovered) from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) * getting registered *after* LBA code has already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) * registered it's distributed lmmio range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (truncate_pat_collision(&iomem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) &(lba_dev->hba.lmmio_space))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) printk(KERN_WARNING "LBA: lmmio_space [%lx/%lx] duplicate!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) (long)lba_dev->hba.lmmio_space.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) (long)lba_dev->hba.lmmio_space.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) lba_dev->hba.lmmio_space.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) pci_add_resource_offset(&resources, &lba_dev->hba.io_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) HBA_PORT_BASE(lba_dev->hba.hba_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (lba_dev->hba.elmmio_space.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) lba_dev->hba.lmmio_space_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (lba_dev->hba.lmmio_space.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) pci_add_resource_offset(&resources, &lba_dev->hba.lmmio_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) lba_dev->hba.lmmio_space_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) if (lba_dev->hba.gmmio_space.flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* Not registering GMMIO space - according to docs it's not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * even used on HP-UX. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* pci_add_resource(&resources, &lba_dev->hba.gmmio_space); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) pci_add_resource(&resources, &lba_dev->hba.bus_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) dev->dev.platform_data = lba_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) lba_bus = lba_dev->hba.hba_bus =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) pci_create_root_bus(&dev->dev, lba_dev->hba.bus_num.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) cfg_ops, NULL, &resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (!lba_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) pci_free_resource_list(&resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) max = pci_scan_child_bus(lba_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /* This is in lieu of calling pci_assign_unassigned_resources() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (is_pdc_pat()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* assign resources to un-initialized devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) DBG_PAT("LBA pci_bus_size_bridges()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) pci_bus_size_bridges(lba_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) DBG_PAT("LBA pci_bus_assign_resources()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) pci_bus_assign_resources(lba_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #ifdef DEBUG_LBA_PAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) DBG_PAT("\nLBA PIOP resource tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) lba_dump_res(&lba_dev->hba.io_space, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) DBG_PAT("\nLBA LMMIO resource tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) lba_dump_res(&lba_dev->hba.lmmio_space, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) ** Once PCI register ops has walked the bus, access to config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ** space is restricted. Avoids master aborts on config cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) ** Early LBA revs go fatal on *any* master abort.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (cfg_ops == &elroy_cfg_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) lba_dev->flags |= LBA_FLAG_SKIP_PROBE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) lba_next_bus = max + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) pci_bus_add_devices(lba_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /* Whew! Finally done! Tell services we got this one covered. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static const struct parisc_device_id lba_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) { HPHW_BRIDGE, HVERSION_REV_ANY_ID, ELROY_HVERS, 0xa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) { HPHW_BRIDGE, HVERSION_REV_ANY_ID, MERCURY_HVERS, 0xa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) { HPHW_BRIDGE, HVERSION_REV_ANY_ID, QUICKSILVER_HVERS, 0xa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static struct parisc_driver lba_driver __refdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .id_table = lba_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .probe = lba_driver_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ** One time initialization to let the world know the LBA was found.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ** Must be called exactly once before pci_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) void __init lba_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) register_parisc_driver(&lba_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ** Initialize the IBASE/IMASK registers for LBA (Elroy).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) ** Only called from sba_iommu.c in order to route ranges (MMIO vs DMA).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) ** sba_iommu is responsible for locking (none needed at init time).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) void lba_set_iregs(struct parisc_device *lba, u32 ibase, u32 imask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) void __iomem * base_addr = ioremap(lba->hpa.start, 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) imask <<= 2; /* adjust for hints - 2 more bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* Make sure we aren't trying to set bits that aren't writeable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) WARN_ON((ibase & 0x001fffff) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) WARN_ON((imask & 0x001fffff) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) DBG("%s() ibase 0x%x imask 0x%x\n", __func__, ibase, imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) WRITE_REG32( imask, base_addr + LBA_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) WRITE_REG32( ibase, base_addr + LBA_IBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) iounmap(base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) * The design of the Diva management card in rp34x0 machines (rp3410, rp3440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * seems rushed, so that many built-in components simply don't work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * The following quirks disable the serial AUX port and the built-in ATI RV100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) * Radeon 7000 graphics card which both don't have any external connectors and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) * thus are useless, and even worse, e.g. the AUX port occupies ttyS0 and as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) * such makes those machines the only PARISC machines on which we can't use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) * ttyS0 as boot console.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static void quirk_diva_ati_card(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) dev->subsystem_device != 0x1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) dev_info(&dev->dev, "Hiding Diva built-in ATI card");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) dev->device = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) quirk_diva_ati_card);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static void quirk_diva_aux_disable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) dev->subsystem_device != 0x1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) dev_info(&dev->dev, "Hiding Diva built-in AUX serial device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) dev->device = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) quirk_diva_aux_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static void quirk_tosca_aux_disable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (dev->subsystem_vendor != PCI_VENDOR_ID_HP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) dev->subsystem_device != 0x104a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) dev_info(&dev->dev, "Hiding Tosca secondary built-in AUX serial device");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) dev->device = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) quirk_tosca_aux_disable);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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