^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Private structs/constants for PARISC IOSAPIC support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2000 Hewlett Packard (Grant Grundler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) ** This file is private to iosapic driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ** If stuff needs to be used by another driver, move it to a common file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ** WARNING: fields most data structures here are ordered to make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ** Interrupt Routing Stuff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ** -----------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ** The interrupt routing table consists of entries derived from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ** MP Specification Draft 1.5. There is one interrupt routing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ** table per cell. N- and L-class consist of a single cell.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct irt_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Entry Type 139 identifies an I/O SAPIC interrupt entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 entry_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Entry Length 16 indicates entry is 16 bytes long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 entry_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ** Interrupt Type of 0 indicates a vectored interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ** all other values are reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 interrupt_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) ** PO and EL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ** Polarity of SAPIC I/O input signals:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ** 00 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ** 01 = Active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ** 10 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ** 11 = Active low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ** Trigger mode of SAPIC I/O input signals:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ** 00 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ** 01 = Edge-triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ** 10 = Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ** 11 = Level-triggered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 polarity_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ** IRQ and DEVNO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ** irq identifies PCI interrupt signal where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ** 0x0 corresponds to INT_A#,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ** 0x1 corresponds to INT_B#,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ** 0x2 corresponds to INT_C#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ** 0x3 corresponds to INT_D#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ** PCI device number where interrupt originates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 src_bus_irq_devno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Source Bus ID identifies the bus where interrupt signal comes from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 src_bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ** Segment ID is unique across a protection domain and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ** identifies a segment of PCI buses (reserved in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ** MP Specification Draft 1.5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 src_seg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ** Destination I/O SAPIC INTIN# identifies the INTIN n pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ** to which the signal is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 dest_iosapic_intin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ** Destination I/O SAPIC Address identifies the I/O SAPIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ** to which the signal is connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u64 dest_iosapic_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IRT_IOSAPIC_TYPE 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IRT_IOSAPIC_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IRT_VECTORED_INTR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IRT_PO_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IRT_ACTIVE_HI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IRT_ACTIVE_LO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IRT_EL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IRT_EL_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IRT_EDGE_TRIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IRT_LEVEL_TRIG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IRT_IRQ_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IRT_DEV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IRT_DEV_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IRT_IRQ_DEVNO_MASK ((IRT_DEV_MASK << IRT_DEV_SHIFT) | IRT_IRQ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #ifdef SUPPORT_MULTI_CELL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct iosapic_irt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct iosapic_irt *irt_next; /* next routing table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct irt_entry *irt_base; /* intr routing table address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) size_t irte_count; /* number of entries in the table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) size_t irte_size; /* size (bytes) of each entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct vector_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct iosapic_info *iosapic; /* I/O SAPIC this vector is on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct irt_entry *irte; /* IRT entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 __iomem *eoi_addr; /* precalculate EOI reg address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 eoi_data; /* IA64: ? PA: swapped txn_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int txn_irq; /* virtual IRQ number for processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ulong txn_addr; /* IA64: id_eid PA: partial HPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 txn_data; /* CPU interrupt bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 status; /* status/flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 irqline; /* INTINn(IRQ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct iosapic_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct iosapic_info * isi_next; /* list of I/O SAPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void __iomem * addr; /* remapped address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long isi_hpa; /* physical base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct vector_info * isi_vector; /* IRdT (IRQ line) array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int isi_num_vectors; /* size of IRdT array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int isi_status; /* status/flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int isi_version; /* DEBUG: data fr version reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #ifdef __IA64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ** PA risc does NOT have any local sapics. IA64 does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ** PIB (Processor Interrupt Block) is handled by Astro or Dew (Stretch CEC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ** PA: Get id_eid from IRT and hardcode PIB to 0xfeeNNNN0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ** Emulate the data on PAT platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct local_sapic_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct local_sapic_info *lsi_next; /* point to next CPU info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int *lsi_cpu_id; /* point to logical CPU id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long *lsi_id_eid; /* point to IA-64 CPU id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int *lsi_status; /* point to CPU status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void *lsi_private; /* point to special info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ** "root" data structure which ties everything together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ** Should always be able to start with sapic_root and locate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ** the desired information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct sapic_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct sapic_info *si_next; /* info is per cell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int si_cellid; /* cell id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int si_status; /* status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) char *si_pib_base; /* intr blk base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) local_sapic_info_t *si_local_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) io_sapic_info_t *si_io_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) extint_info_t *si_extint_info;/* External Intr info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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