Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * drivers/parisc/gsc.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Declarations for functions in gsc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2000-2002 Helge Deller, Matthew Wilcox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/parisc-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define OFFSET_IRR 0x0000   /* Interrupt request register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define OFFSET_IMR 0x0004   /* Interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define OFFSET_IPR 0x0008   /* Interrupt pending register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OFFSET_ICR 0x000C   /* Interrupt control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OFFSET_IAR 0x0010   /* Interrupt address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* PA I/O Architected devices support at least 5 bits in the EIM register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GSC_EIM_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct gsc_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	unsigned long txn_addr;	/* IRQ "target" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	int txn_data;		/* HW "IRQ" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	int irq;		/* virtual IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct gsc_asic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	struct parisc_device *gsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	unsigned long hpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	int eim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	int global_irq[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int gsc_common_setup(struct parisc_device *parent, struct gsc_asic *gsc_asic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int gsc_alloc_irq(struct gsc_irq *dev);			/* dev needs an irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int gsc_claim_irq(struct gsc_irq *dev, int irq);	/* dev needs this irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int gsc_assign_irq(struct irq_chip *type, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int gsc_find_local_irq(unsigned int irq, int *global_irq, int limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void gsc_fixup_irqs(struct parisc_device *parent, void *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		void (*choose)(struct parisc_device *child, void *ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void gsc_asic_assign_irq(struct gsc_asic *asic, int local_irq, int *irqp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) irqreturn_t gsc_asic_intr(int irq, void *dev);