Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Interrupt management for most GSC and related devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * (c) Copyright 1999 Alex deVries for The Puffin Group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * (c) Copyright 1999 Grant Grundler for Hewlett-Packard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * (c) Copyright 1999 Matthew Wilcox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * (c) Copyright 2000 Helge Deller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * (c) Copyright 2001 Matthew Wilcox for Hewlett-Packard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "gsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DEBPRINTK printk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DEBPRINTK(x,...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) int gsc_alloc_irq(struct gsc_irq *i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	int irq = txn_alloc_irq(GSC_EIM_WIDTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		printk("cannot get irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	i->txn_addr = txn_alloc_addr(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	i->txn_data = txn_alloc_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	i->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) int gsc_claim_irq(struct gsc_irq *i, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int c = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	irq += CPU_IRQ_BASE; /* virtualize the IRQ first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	irq = txn_claim_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		printk("cannot claim irq %d\n", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	i->txn_addr = txn_alloc_addr(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	i->txn_data = txn_alloc_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	i->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) EXPORT_SYMBOL(gsc_alloc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) EXPORT_SYMBOL(gsc_claim_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* Common interrupt demultiplexer used by Asp, Lasi & Wax.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) irqreturn_t gsc_asic_intr(int gsc_asic_irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	unsigned long irr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct gsc_asic *gsc_asic = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	irr = gsc_readl(gsc_asic->hpa + OFFSET_IRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (irr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	DEBPRINTK("%s intr, mask=0x%x\n", gsc_asic->name, irr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		int local_irq = __ffs(irr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		unsigned int irq = gsc_asic->global_irq[local_irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		irr &= ~(1 << local_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	} while (irr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) int gsc_find_local_irq(unsigned int irq, int *global_irqs, int limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int local_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	for (local_irq = 0; local_irq < limit; local_irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		if (global_irqs[local_irq] == irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			return local_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	return NO_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void gsc_asic_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct gsc_asic *irq_dev = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int local_irq = gsc_find_local_irq(d->irq, irq_dev->global_irq, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, d->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			irq_dev->name, imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* Disable the IRQ line by clearing the bit in the IMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	imr = gsc_readl(irq_dev->hpa + OFFSET_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	imr &= ~(1 << local_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	gsc_writel(imr, irq_dev->hpa + OFFSET_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void gsc_asic_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct gsc_asic *irq_dev = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int local_irq = gsc_find_local_irq(d->irq, irq_dev->global_irq, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	DEBPRINTK(KERN_DEBUG "%s(%d) %s: IMR 0x%x\n", __func__, d->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			irq_dev->name, imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* Enable the IRQ line by setting the bit in the IMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	imr = gsc_readl(irq_dev->hpa + OFFSET_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	imr |= 1 << local_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	gsc_writel(imr, irq_dev->hpa + OFFSET_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 * FIXME: read IPR to make sure the IRQ isn't already pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 *   If so, we need to read IRR and manually call do_irq().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct irq_chip gsc_asic_interrupt_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.name		=	"GSC-ASIC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.irq_unmask	=	gsc_asic_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.irq_mask	=	gsc_asic_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int gsc_assign_irq(struct irq_chip *type, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	static int irq = GSC_IRQ_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	if (irq > GSC_IRQ_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		return NO_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	irq_set_chip_and_handler(irq, type, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	irq_set_chip_data(irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	return irq++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void gsc_asic_assign_irq(struct gsc_asic *asic, int local_irq, int *irqp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int irq = asic->global_irq[local_irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (irq <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		irq = gsc_assign_irq(&gsc_asic_interrupt_type, asic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		if (irq == NO_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		asic->global_irq[local_irq] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	*irqp = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct gsc_fixup_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	void (*choose_irq)(struct parisc_device *, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	void *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int gsc_fixup_irqs_callback(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct parisc_device *padev = to_parisc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct gsc_fixup_struct *gf = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	/* work-around for 715/64 and others which have parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	   at path [5] and children at path [5/0/x] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (padev->id.hw_type == HPHW_FAULTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		gsc_fixup_irqs(padev, gf->ctrl, gf->choose_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	gf->choose_irq(padev, gf->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void gsc_fixup_irqs(struct parisc_device *parent, void *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			void (*choose_irq)(struct parisc_device *, void *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct gsc_fixup_struct data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.choose_irq	= choose_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.ctrl		= ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	device_for_each_child(&parent->dev, &data, gsc_fixup_irqs_callback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int gsc_common_setup(struct parisc_device *parent, struct gsc_asic *gsc_asic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	gsc_asic->gsc = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* Initialise local irq -> global irq mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	for (i = 0; i < 32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		gsc_asic->global_irq[i] = NO_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* allocate resource region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	res = request_mem_region(gsc_asic->hpa, 0x100000, gsc_asic->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		res->flags = IORESOURCE_MEM; 	/* do not mark it busy ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	printk(KERN_WARNING "%s IRQ %d EIM 0x%x", gsc_asic->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			parent->irq, gsc_asic->eim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (gsc_readl(gsc_asic->hpa + OFFSET_IMR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		printk("  IMR is non-zero! (0x%x)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 				gsc_readl(gsc_asic->hpa + OFFSET_IMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) extern struct parisc_driver lasi_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) extern struct parisc_driver asp_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) extern struct parisc_driver wax_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void __init gsc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #ifdef CONFIG_GSC_LASI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	register_parisc_driver(&lasi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	register_parisc_driver(&asp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #ifdef CONFIG_GSC_WAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	register_parisc_driver(&wax_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }