^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ** DINO manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ** (c) Copyright 1999 Red Hat Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) ** (c) Copyright 1999 SuSE GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) ** (c) Copyright 1999,2000 Hewlett-Packard Company
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ** (c) Copyright 2000 Grant Grundler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) ** (c) Copyright 2006-2019 Helge Deller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) ** This module provides access to Dino PCI bus (config/IOport spaces)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ** and helps manage Dino IRQ lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ** Dino interrupt handling is a bit complicated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ** Dino always writes to the broadcast EIR via irr0 for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ** (BIG WARNING: using broadcast EIR is a really bad thing for SMP!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ** Only one processor interrupt is used for the 11 IRQ line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ** inputs to dino.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ** The different between Built-in Dino and Card-Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ** dino is in chip initialization and pci device initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ** Linux drivers can only use Card-Mode Dino if pci devices I/O port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ** BARs are configured and used by the driver. Programming MMIO address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ** requires substantial knowledge of available Host I/O address ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ** is currently not supported. Port/Config accessor functions are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ** same. "BIOS" differences are handled within the existing routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Changes :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ** 2001-06-14 : Clement Moyroud (moyroudc@esiee.fr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ** - added support for the integrated RS232.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ** TODO: create a virtual address for each Dino HPA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ** GSC code might be able to do this since IODC data tells us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ** how many pages are used. PCI subsystem could (must?) do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ** for PCI drivers devices which implement/use MMIO registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/interrupt.h> /* for struct irqaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/spinlock.h> /* for spinlock_t and prototypes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <asm/pdc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <asm/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "gsc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include "iommu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #undef DINO_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef DINO_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DBG(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DBG(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ** Config accessor functions only pass in the 8-bit bus number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ** and not the 8-bit "PCI Segment" number. Each Dino will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ** assigned a PCI bus number based on "when" it's discovered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ** The "secondary" bus number is set to this before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ** pci_scan_bus(). If any PPB's are present, the scan will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ** discover them and update the "secondary" and "subordinate"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ** fields in Dino's pci_bus structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ** Changes in the configuration *will* result in a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ** bus number for each dino.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define is_card_dino(id) ((id)->hw_type == HPHW_A_DMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define is_cujo(id) ((id)->hversion == 0x682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DINO_IAR0 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DINO_IODC_ADDR 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DINO_IODC_DATA_0 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DINO_IODC_DATA_1 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DINO_IRR0 0x00C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DINO_IAR1 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DINO_IRR1 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DINO_IMR 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DINO_IPR 0x01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DINO_TOC_ADDR 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DINO_ICR 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DINO_ILR 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DINO_IO_COMMAND 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DINO_IO_STATUS 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DINO_IO_CONTROL 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DINO_IO_GSC_ERR_RESP 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DINO_IO_ERR_INFO 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DINO_IO_PCI_ERR_RESP 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DINO_IO_FBB_EN 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DINO_IO_ADDR_EN 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DINO_PCI_ADDR 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DINO_CONFIG_DATA 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DINO_IO_DATA 0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DINO_MEM_DATA 0x070 /* Dino 3.x only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DINO_GSC2X_CONFIG 0x7b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DINO_GMASK 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DINO_PAMR 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DINO_PAPR 0x808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DINO_DAMODE 0x80c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DINO_PCICMD 0x810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DINO_PCISTS 0x814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DINO_MLTIM 0x81c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DINO_BRDG_FEAT 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DINO_PCIROR 0x824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DINO_PCIWOR 0x828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DINO_TLTIM 0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DINO_IRQS 11 /* bits 0-10 are architected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DINO_LOCAL_IRQS (DINO_IRQS+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DINO_MASK_IRQ(x) (1<<(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCIINTA 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PCIINTB 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PCIINTC 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PCIINTD 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PCIINTE 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PCIINTF 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GSCEXTINT 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* #define xxx 0x080 - bit 7 is "default" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* #define xxx 0x100 - bit 8 not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* #define xxx 0x200 - bit 9 not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RS232INT 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct dino_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct pci_hba_data hba; /* 'C' inheritance - must be first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) spinlock_t dinosaur_pen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long txn_addr; /* EIR addr to generate interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 txn_data; /* EIR data assign to each dino */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 imr; /* IRQ's which are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int global_irq[DINO_LOCAL_IRQS]; /* map IMR bit to global irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifdef DINO_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int dino_irr0; /* save most recent IRQ line stat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline struct dino_device *DINO_DEV(struct pci_hba_data *hba)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return container_of(hba, struct dino_device, hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Dino Configuration Space Accessor Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DINO_CFG_TOK(bus,dfn,pos) ((u32) ((bus)<<16 | (dfn)<<8 | (pos)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * keep the current highest bus count to assist in allocating busses. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * tries to keep a global bus count total so that when we discover an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * entirely new bus, it can be given a unique bus number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int dino_current_bus = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int dino_cfg_read(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int size, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void __iomem *base_addr = d->hba.base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) spin_lock_irqsave(&d->dinosaur_pen, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* tell HW which CFG address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __raw_writel(v, base_addr + DINO_PCI_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* generate cfg read cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (size == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *val = readb(base_addr + DINO_CONFIG_DATA + (where & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } else if (size == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) *val = readw(base_addr + DINO_CONFIG_DATA + (where & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } else if (size == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *val = readl(base_addr + DINO_CONFIG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spin_unlock_irqrestore(&d->dinosaur_pen, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * Dino address stepping "feature":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * When address stepping, Dino attempts to drive the bus one cycle too soon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * even though the type of cycle (config vs. MMIO) might be different.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * The read of Ven/Prod ID is harmless and avoids Dino's address stepping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int dino_cfg_write(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int size, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct dino_device *d = DINO_DEV(parisc_walk_tree(bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 local_bus = (bus->parent == NULL) ? 0 : bus->busn_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 v = DINO_CFG_TOK(local_bus, devfn, where & ~3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void __iomem *base_addr = d->hba.base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DBG("%s: %p, %d, %d, %d\n", __func__, base_addr, devfn, where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spin_lock_irqsave(&d->dinosaur_pen, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* avoid address stepping feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __raw_readl(base_addr + DINO_CONFIG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* tell HW which CFG address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __raw_writel(v, base_addr + DINO_PCI_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* generate cfg read cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (size == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) writeb(val, base_addr + DINO_CONFIG_DATA + (where & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else if (size == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) writew(val, base_addr + DINO_CONFIG_DATA + (where & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) } else if (size == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writel(val, base_addr + DINO_CONFIG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) spin_unlock_irqrestore(&d->dinosaur_pen, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct pci_ops dino_cfg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .read = dino_cfg_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .write = dino_cfg_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Dino "I/O Port" Space Accessor Functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * Many PCI devices don't require use of I/O port space (eg Tulip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * NCR720) since they export the same registers to both MMIO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * I/O port space. Performance is going to stink if drivers use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * I/O port instead of MMIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DINO_PORT_IN(type, size, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static u##size dino_in##size (struct pci_hba_data *d, u16 addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u##size v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned long flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* tell HW which IO Port address */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* generate I/O PORT read cycle */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) v = read##type(d->base_addr+DINO_IO_DATA+(addr&mask)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DINO_PORT_IN(b, 8, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DINO_PORT_IN(w, 16, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DINO_PORT_IN(l, 32, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DINO_PORT_OUT(type, size, mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void dino_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spin_lock_irqsave(&(DINO_DEV(d)->dinosaur_pen), flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* tell HW which IO port address */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* generate cfg write cycle */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) write##type(val, d->base_addr+DINO_IO_DATA+(addr&mask)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) spin_unlock_irqrestore(&(DINO_DEV(d)->dinosaur_pen), flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DINO_PORT_OUT(b, 8, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DINO_PORT_OUT(w, 16, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DINO_PORT_OUT(l, 32, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct pci_port_ops dino_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .inb = dino_in8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .inw = dino_in16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .inl = dino_in32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .outb = dino_out8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .outw = dino_out16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .outl = dino_out32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void dino_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Clear the matching bit in the IMR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dino_dev->imr &= ~(DINO_MASK_IRQ(local_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void dino_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct dino_device *dino_dev = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int local_irq = gsc_find_local_irq(d->irq, dino_dev->global_irq, DINO_LOCAL_IRQS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DBG(KERN_WARNING "%s(0x%px, %d)\n", __func__, dino_dev, d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ** clear pending IRQ bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ** This does NOT change ILR state!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ** See comment below for ILR usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) __raw_readl(dino_dev->hba.base_addr+DINO_IPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* set the matching bit in the IMR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dino_dev->imr |= DINO_MASK_IRQ(local_irq); /* used in dino_isr() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* Emulate "Level Triggered" Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ** Basically, a driver is blowing it if the IRQ line is asserted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ** while the IRQ is disabled. But tulip.c seems to do that....
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ** Give 'em a kluge award and a nice round of applause!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ** The gsc_write will generate an interrupt which invokes dino_isr().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ** dino_isr() will read IPR and find nothing. But then catch this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ** when it also checks ILR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) tmp = __raw_readl(dino_dev->hba.base_addr+DINO_ILR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (tmp & DINO_MASK_IRQ(local_irq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DBG(KERN_WARNING "%s(): IRQ asserted! (ILR 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) __func__, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) gsc_writel(dino_dev->txn_data, dino_dev->txn_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static struct irq_chip dino_interrupt_type = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .name = "GSC-PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .irq_unmask = dino_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .irq_mask = dino_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Handle a Processor interrupt generated by Dino.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * ilr_loop counter is a kluge to prevent a "stuck" IRQ line from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * wedging the CPU. Could be removed or made optional at some point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static irqreturn_t dino_isr(int irq, void *intr_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct dino_device *dino_dev = intr_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ilr_loop = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* read and acknowledge pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #ifdef DINO_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dino_dev->dino_irr0 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mask = __raw_readl(dino_dev->hba.base_addr+DINO_IRR0) & DINO_IRR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ilr_again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int local_irq = __ffs(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int irq = dino_dev->global_irq[local_irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DBG(KERN_DEBUG "%s(%d, %p) mask 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) __func__, irq, intr_dev, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mask &= ~DINO_MASK_IRQ(local_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } while (mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Support for level triggered IRQ lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ** Dropping this support would make this routine *much* faster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ** But since PCI requires level triggered IRQ line to share lines...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ** device drivers may assume lines are level triggered (and not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ** edge triggered like EISA/ISA can be).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mask = __raw_readl(dino_dev->hba.base_addr+DINO_ILR) & dino_dev->imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (--ilr_loop > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto ilr_again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pr_warn_ratelimited("Dino 0x%px: stuck interrupt %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dino_dev->hba.base_addr, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static void dino_assign_irq(struct dino_device *dino, int local_irq, int *irqp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int irq = gsc_assign_irq(&dino_interrupt_type, dino);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (irq == NO_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *irqp = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dino->global_irq[local_irq] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void dino_choose_irq(struct parisc_device *dev, void *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct dino_device *dino = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) switch (dev->id.sversion) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) case 0x00084: irq = 8; break; /* PS/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case 0x0008c: irq = 10; break; /* RS232 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case 0x00096: irq = 8; break; /* PS/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) default: return; /* Unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dino_assign_irq(dino, irq, &dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * Cirrus 6832 Cardbus reports wrong irq on RDI Tadpole PARISC Laptop (deller@gmx.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * (the irqs are off-by-one, not sure yet if this is a cirrus, dino-hardware or dino-driver problem...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static void quirk_cirrus_cardbus(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u8 new_irq = dev->irq - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) printk(KERN_INFO "PCI: Cirrus Cardbus IRQ fixup for %s, from %d to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pci_name(dev), dev->irq, new_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev->irq = new_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832, quirk_cirrus_cardbus );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #ifdef CONFIG_TULIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* Check if PCI device is behind a Card-mode Dino. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int pci_dev_is_behind_card_dino(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct dino_device *dino_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dino_dev = DINO_DEV(parisc_walk_tree(dev->bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return is_card_dino(&dino_dev->hba.dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static void pci_fixup_tulip(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (!pci_dev_is_behind_card_dino(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pr_warn("%s: HP HSC-PCI Cards with card-mode Dino not yet supported.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Disable this card by zeroing the PCI resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) memset(&dev->resource[0], 0, sizeof(dev->resource[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) memset(&dev->resource[1], 0, sizeof(dev->resource[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_DEC, PCI_ANY_ID, pci_fixup_tulip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #endif /* CONFIG_TULIP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dino_bios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DBG("dino_bios_init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * dino_card_setup - Set up the memory space for a Dino in card mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * @bus: the bus under this dino
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * Claim an 8MB chunk of unused IO space and call the generic PCI routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * to set up the addresses of the devices on this bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define _8MB 0x00800000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dino_card_setup(struct pci_bus *bus, void __iomem *base_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) char name[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) res = &dino_dev->hba.lmmio_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_name(bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) res->name = kmalloc(size+1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if(res->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) strcpy((char *)res->name, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) res->name = dino_dev->hba.lmmio_space.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ccio_allocate_resource(dino_dev->hba.dev, res, _8MB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) F_EXTEND(0xf0000000UL) | _8MB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) F_EXTEND(0xffffffffUL) &~ _8MB, _8MB) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct pci_dev *dev, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) printk(KERN_ERR "Dino: cannot attach bus %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_name(bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* kill the bus, we can't do anything with it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) list_del(&dev->bus_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bus->resource[1] = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) bus->resource[0] = &(dino_dev->hba.io_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Now tell dino what range it has */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) for (i = 1; i < 31; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (res->start == F_EXTEND(0xf0000000UL | (i * _8MB)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) DBG("DINO GSC WRITE i=%d, start=%lx, dino addr = %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) i, res->start, base_addr + DINO_IO_ADDR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) dino_card_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 irq_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ** REVISIT: card-mode PCI-PCI expansion chassis do exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ** Not sure they were ever productized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ** Die here since we'll die later in dino_inb() anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) panic("Card-Mode Dino: PCI-PCI Bridge not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ** Set Latency Timer to 0xff (not a shared bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ** Set CACHELINE_SIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dino_cfg_write(dev->bus, dev->devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PCI_CACHE_LINE_SIZE, 2, 0xff00 | L1_CACHE_BYTES/4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ** Program INT_LINE for card-mode devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ** The cards are hardwired according to this algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ** And it doesn't matter if PPB's are present or not since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ** the IRQ lines bypass the PPB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ** "-1" converts INTA-D (1-4) to PCIINTA-D (0-3) range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ** The additional "-1" adjusts for skewing the IRQ<->slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dino_cfg_read(dev->bus, dev->devfn, PCI_INTERRUPT_PIN, 1, &irq_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev->irq = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Shouldn't really need to do this but it's in case someone tries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ** to bypass PCI services and look at the card themselves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dino_cfg_write(dev->bus, dev->devfn, PCI_INTERRUPT_LINE, 1, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* The alignment contraints for PCI bridges under dino */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define DINO_BRIDGE_ALIGN 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dino_fixup_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct dino_device *dino_dev = DINO_DEV(parisc_walk_tree(bus->bridge));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) DBG(KERN_WARNING "%s(0x%px) bus %d platform_data 0x%px\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) __func__, bus, bus->busn_res.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bus->bridge->platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Firmware doesn't set up card-mode dino, so we have to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (is_card_dino(&dino_dev->hba.dev->id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dino_card_setup(bus, dino_dev->hba.base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) } else if (bus->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pci_read_bridge_bases(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) for(i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if((bus->self->resource[i].flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) (IORESOURCE_IO | IORESOURCE_MEM)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if(bus->self->resource[i].flags & IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* There's a quirk to alignment of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * bridge memory resources: the start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * is the alignment and start-end is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * the size. However, firmware will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * have assigned start and end, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * need to take this into account */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) bus->self->resource[i].end = bus->self->resource[i].end - bus->self->resource[i].start + DINO_BRIDGE_ALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) bus->self->resource[i].start = DINO_BRIDGE_ALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DBG("DEBUG %s assigning %d [%pR]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev_name(&bus->self->dev), i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) &bus->self->resource[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) WARN_ON(pci_assign_resource(bus->self, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) DBG("DEBUG %s after assign %d [%pR]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_name(&bus->self->dev), i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) &bus->self->resource[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (is_card_dino(&dino_dev->hba.dev->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dino_card_fixup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ** P2PB's only have 2 BARs, no IRQs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ** I'd like to just ignore them for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) pcibios_init_bridge(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* null out the ROM resource if there is one (we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * care about an expansion rom on parisc, since it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * usually contains (x86) bios code) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev->resource[PCI_ROM_RESOURCE].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if(dev->irq == 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define DINO_FIX_UNASSIGNED_INTERRUPTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #ifdef DINO_FIX_UNASSIGNED_INTERRUPTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* This code tries to assign an unassigned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * interrupt. Leave it disabled unless you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * *really* know what you're doing since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * pin<->interrupt line mapping varies by bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * and machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u32 irq_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dino_cfg_read(dev->bus, dev->devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PCI_INTERRUPT_PIN, 1, &irq_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) irq_pin = pci_swizzle_interrupt_pin(dev, irq_pin) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) printk(KERN_WARNING "Device %s has undefined IRQ, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "setting to %d\n", pci_name(dev), irq_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dino_cfg_write(dev->bus, dev->devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PCI_INTERRUPT_LINE, 1, irq_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dino_assign_irq(dino_dev, irq_pin, &dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev->irq = 65535;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) printk(KERN_WARNING "Device %s has unassigned IRQ\n", pci_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Adjust INT_LINE for that busses region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dino_assign_irq(dino_dev, dev->irq, &dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static struct pci_bios_ops dino_bios_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .init = dino_bios_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .fixup_bus = dino_fixup_bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * Initialise a DINO controller chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dino_card_init(struct dino_device *dino_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 brdg_feat = 0x00784e05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) status = __raw_readl(dino_dev->hba.base_addr+DINO_IO_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (status & 0x0000ff80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __raw_writel(0x00000005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dino_dev->hba.base_addr+DINO_IO_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) __raw_writel(0x00000001, dino_dev->hba.base_addr+DINO_IO_FBB_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* REVISIT - should be a runtime check (eg if (CPU_IS_PCX_L) ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ** PCX-L processors don't support XQL like Dino wants it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ** PCX-L2 ignore XQL signal and it doesn't matter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) brdg_feat &= ~0x4; /* UXQL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) __raw_writel( brdg_feat, dino_dev->hba.base_addr+DINO_BRDG_FEAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ** Don't enable address decoding until we know which I/O range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ** currently is available from the host. Only affects MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ** and not I/O port space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_IO_ADDR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_DAMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __raw_writel(0x00222222, dino_dev->hba.base_addr+DINO_PCIWOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) __raw_writel(0x00000040, dino_dev->hba.base_addr+DINO_MLTIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) __raw_writel(0x00000080, dino_dev->hba.base_addr+DINO_IO_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) __raw_writel(0x0000008c, dino_dev->hba.base_addr+DINO_TLTIM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Disable PAMR before writing PAPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) __raw_writel(0x0000007e, dino_dev->hba.base_addr+DINO_PAMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) __raw_writel(0x0000007f, dino_dev->hba.base_addr+DINO_PAPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_PAMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ** Dino ERS encourages enabling FBB (0x6f).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ** We can't until we know *all* devices below us can support it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ** (Something in device configuration header tells us).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __raw_writel(0x0000004f, dino_dev->hba.base_addr+DINO_PCICMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* Somewhere, the PCI spec says give devices 1 second
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ** to recover from the #RESET being de-asserted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ** Experience shows most devices only need 10ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ** This short-cut speeds up booting significantly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) mdelay(pci_post_reset_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dino_bridge_init(struct dino_device *dino_dev, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) unsigned long io_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int result, i, count=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct resource *res, *prevres = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * Decoding IO_ADDR_EN only works for Built-in Dino
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * since PDC has already initialized this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) io_addr = __raw_readl(dino_dev->hba.base_addr + DINO_IO_ADDR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (io_addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) printk(KERN_WARNING "%s: No PCI devices enabled.\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) res = &dino_dev->hba.lmmio_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) for (i = 0; i < 32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) unsigned long start, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if((io_addr & (1 << i)) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) start = F_EXTEND(0xf0000000UL) | (i << 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) end = start + 8 * 1024 * 1024 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) DBG("DINO RANGE %d is at 0x%lx-0x%lx\n", count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if(prevres && prevres->end + 1 == start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) prevres->end = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if(count >= DINO_MAX_LMMIO_RESOURCES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) printk(KERN_ERR "%s is out of resource windows for range %d (0x%lx-0x%lx)\n", name, count, start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) prevres = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) res->start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) res->end = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) res->name = kmalloc(64, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if(res->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) snprintf((char *)res->name, 64, "%s LMMIO %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) name, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) res++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) res = &dino_dev->hba.lmmio_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) for(i = 0; i < DINO_MAX_LMMIO_RESOURCES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if(res[i].flags == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) result = ccio_request_resource(dino_dev->hba.dev, &res[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) printk(KERN_ERR "%s: failed to claim PCI Bus address "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "space %d (%pR)!\n", name, i, &res[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int __init dino_common_init(struct parisc_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct dino_device *dino_dev, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u32 eim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct gsc_irq gsc_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) pcibios_register_hba(&dino_dev->hba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) pci_bios = &dino_bios_ops; /* used by pci_scan_bus() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pci_port = &dino_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ** Note: SMP systems can make use of IRR1/IAR1 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ** But it won't buy much performance except in very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ** specific applications/configurations. Note Dino
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ** still only has 11 IRQ input lines - just map some of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ** to a different processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dev->irq = gsc_alloc_irq(&gsc_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dino_dev->txn_addr = gsc_irq.txn_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dino_dev->txn_data = gsc_irq.txn_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) eim = ((u32) gsc_irq.txn_addr) | gsc_irq.txn_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ** Dino needs a PA "IRQ" to get a processor's attention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ** arch/parisc/kernel/irq.c returns an EIRR bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (dev->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) printk(KERN_WARNING "%s: gsc_alloc_irq() failed\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) status = request_irq(dev->irq, dino_isr, 0, name, dino_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) printk(KERN_WARNING "%s: request_irq() failed with %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Support the serial port which is sometimes attached on built-in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * Dino / Cujo chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) gsc_fixup_irqs(dev, dino_dev, dino_choose_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ** This enables DINO to generate interrupts when it sees
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ** any of its inputs *change*. Just asserting an IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ** before it's enabled (ie unmasked) isn't good enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) __raw_writel(eim, dino_dev->hba.base_addr+DINO_IAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ** Some platforms don't clear Dino's IRR0 register at boot time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ** Reading will clear it now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) __raw_readl(dino_dev->hba.base_addr+DINO_IRR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* allocate I/O Port resource region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) res = &dino_dev->hba.io_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!is_cujo(&dev->id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) res->name = "Dino I/O Port";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) res->name = "Cujo I/O Port";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) res->start = HBA_PORT_BASE(dino_dev->hba.hba_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) res->end = res->start + (HBA_PORT_SPACE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) res->flags = IORESOURCE_IO; /* do not mark it busy ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (request_resource(&ioport_resource, res) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) printk(KERN_ERR "%s: request I/O Port region failed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) "0x%lx/%lx (hpa 0x%px)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) name, (unsigned long)res->start, (unsigned long)res->end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dino_dev->hba.base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define CUJO_RAVEN_ADDR F_EXTEND(0xf1000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define CUJO_FIREHAWK_ADDR F_EXTEND(0xf1604000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define CUJO_RAVEN_BADPAGE 0x01003000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define CUJO_FIREHAWK_BADPAGE 0x01607000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const char dino_vers[][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "2.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) "2.1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "3.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) "3.1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const char cujo_vers[][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) "1.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) "2.0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) void ccio_cujo20_fixup(struct parisc_device *dev, u32 iovp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ** Determine if dino should claim this chip (return 0) or not (return 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ** If so, initialize the chip appropriately (card-mode vs bridge mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ** Much of the initialization is common though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int __init dino_probe(struct parisc_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct dino_device *dino_dev; // Dino specific control struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) const char *version = "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int is_cujo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) LIST_HEAD(resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) unsigned long hpa = dev->hpa.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) name = "Dino";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (is_card_dino(&dev->id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) version = "3.x (card mode)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (!is_cujo(&dev->id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (dev->id.hversion_rev < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) version = dino_vers[dev->id.hversion_rev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) name = "Cujo";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) is_cujo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (dev->id.hversion_rev < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) version = cujo_vers[dev->id.hversion_rev];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) printk("%s version %s found at 0x%lx\n", name, version, hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!request_mem_region(hpa, PAGE_SIZE, name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) printk(KERN_ERR "DINO: Hey! Someone took my MMIO space (0x%lx)!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* Check for bugs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (is_cujo && dev->id.hversion_rev == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #ifdef CONFIG_IOMMU_CCIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) printk(KERN_WARNING "Enabling Cujo 2.0 bug workaround\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (hpa == (unsigned long)CUJO_RAVEN_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ccio_cujo20_fixup(dev, CUJO_RAVEN_BADPAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) } else if (hpa == (unsigned long)CUJO_FIREHAWK_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ccio_cujo20_fixup(dev, CUJO_FIREHAWK_BADPAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) printk("Don't recognise Cujo at address 0x%lx, not enabling workaround\n", hpa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) } else if (!is_cujo && !is_card_dino(&dev->id) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dev->id.hversion_rev < 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) printk(KERN_WARNING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) "The GSCtoPCI (Dino hrev %d) bus converter found may exhibit\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) "data corruption. See Service Note Numbers: A4190A-01, A4191A-01.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) "Systems shipped after Aug 20, 1997 will not exhibit this problem.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) "Models affected: C180, C160, C160L, B160L, and B132L workstations.\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev->id.hversion_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* REVISIT: why are C200/C240 listed in the README table but not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ** "Models affected"? Could be an omission in the original literature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dino_dev = kzalloc(sizeof(struct dino_device), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (!dino_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) printk("dino_init_chip - couldn't alloc dino_device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dino_dev->hba.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dino_dev->hba.base_addr = ioremap(hpa, 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) dino_dev->hba.lmmio_space_offset = PCI_F_EXTEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) spin_lock_init(&dino_dev->dinosaur_pen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dino_dev->hba.iommu = ccio_get_iommu(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (is_card_dino(&dev->id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) dino_card_init(dino_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dino_bridge_init(dino_dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (dino_common_init(dev, dino_dev, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dev->dev.platform_data = dino_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) pci_add_resource_offset(&resources, &dino_dev->hba.io_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) HBA_PORT_BASE(dino_dev->hba.hba_num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (dino_dev->hba.lmmio_space.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) pci_add_resource_offset(&resources, &dino_dev->hba.lmmio_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) dino_dev->hba.lmmio_space_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (dino_dev->hba.elmmio_space.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pci_add_resource_offset(&resources, &dino_dev->hba.elmmio_space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dino_dev->hba.lmmio_space_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (dino_dev->hba.gmmio_space.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) pci_add_resource(&resources, &dino_dev->hba.gmmio_space);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dino_dev->hba.bus_num.start = dino_current_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dino_dev->hba.bus_num.end = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dino_dev->hba.bus_num.flags = IORESOURCE_BUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) pci_add_resource(&resources, &dino_dev->hba.bus_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ** It's not used to avoid chicken/egg problems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ** with configuration accessor functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dino_dev->hba.hba_bus = bus = pci_create_root_bus(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) dino_current_bus, &dino_cfg_ops, NULL, &resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (!bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (duplicate bus number %d?)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) dev_name(&dev->dev), dino_current_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) pci_free_resource_list(&resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* increment the bus number in case of duplicates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dino_current_bus++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) max = pci_scan_child_bus(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) pci_bus_update_busn_res_end(bus, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* This code *depends* on scanning being single threaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * if it isn't, this global bus number count will fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dino_current_bus = max + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pci_bus_assign_resources(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) pci_bus_add_devices(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * Normally, we would just test sversion. But the Elroy PCI adapter has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * the same sversion as Dino, so we have to check hversion as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * Unfortunately, the J2240 PDC reports the wrong hversion for the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * Dino, so we have to test for Dino, Cujo and Dino-in-a-J2240.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * For card-mode Dino, most machines report an sversion of 9D. But 715
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * and 725 firmware misreport it as 0x08080 for no adequately explained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * reason.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static const struct parisc_device_id dino_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) { HPHW_A_DMA, HVERSION_REV_ANY_ID, 0x004, 0x0009D },/* Card-mode Dino */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) { HPHW_A_DMA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x08080 }, /* XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x680, 0xa }, /* Bridge-mode Dino */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x682, 0xa }, /* Bridge-mode Cujo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) { HPHW_BRIDGE, HVERSION_REV_ANY_ID, 0x05d, 0xa }, /* Dino in a J2240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static struct parisc_driver dino_driver __refdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .name = "dino",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .id_table = dino_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .probe = dino_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * One time initialization to let the world know Dino is here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * This is the only routine which is NOT static.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * Must be called exactly once before pci_init().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) int __init dino_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) register_parisc_driver(&dino_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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