^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ** ccio-dma.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) ** DMA management routines for first generation cache-coherent machines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) ** Program U2/Uturn in "Virtual Mode" and use the I/O MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) ** (c) Copyright 2000 Grant Grundler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) ** (c) Copyright 2000 Ryan Bradetich
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) ** (c) Copyright 2000 Hewlett-Packard Company
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ** "Real Mode" operation refers to U2/Uturn chip operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ** U2/Uturn were designed to perform coherency checks w/o using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ** the I/O MMU - basically what x86 does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ** Philipp Rumpf has a "Real Mode" driver for PCX-W machines at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) ** CVSROOT=:pserver:anonymous@198.186.203.37:/cvsroot/linux-parisc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) ** cvs -z3 co linux/arch/parisc/kernel/dma-rm.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ** I've rewritten his code to work under TPG's tree. See ccio-rm-dma.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ** Drawbacks of using Real Mode are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ** o Ability to do scatter/gather in HW is lost.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ** o Doesn't work under PCX-U/U+ machines since they didn't follow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ** the coherency design originally worked out. Only PCX-W does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/proc_fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/dma-map-ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/iommu-helper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/cache.h> /* for L1_CACHE_BYTES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <asm/hardware.h> /* for register_module() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <asm/parisc-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include "iommu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ** Choose "ccio" since that's what HP-UX calls it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ** Make it easier for folks to migrate from one to the other :^)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MODULE_NAME "ccio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #undef DEBUG_CCIO_RES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #undef DEBUG_CCIO_RUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #undef DEBUG_CCIO_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #undef DEBUG_CCIO_RUN_SG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* depends on proc fs support. But costs CPU performance. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #undef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <asm/runway.h> /* for proc_runway_root */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifdef DEBUG_CCIO_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DBG_INIT(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DBG_INIT(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef DEBUG_CCIO_RUN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DBG_RUN(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DBG_RUN(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #ifdef DEBUG_CCIO_RES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DBG_RES(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DBG_RES(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef DEBUG_CCIO_RUN_SG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DBG_RUN_SG(x...) printk(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DBG_RUN_SG(x...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CCIO_INLINE inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define WRITE_U32(value, addr) __raw_writel(value, addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define READ_U32(addr) __raw_readl(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define U2_IOA_RUNWAY 0x580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define U2_BC_GSC 0x501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define UTURN_IOA_RUNWAY 0x581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define UTURN_BC_GSC 0x502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IOA_NORMAL_MODE 0x00020080 /* IO_CONTROL to turn on CCIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CMD_TLB_DIRECT_WRITE 35 /* IO_COMMAND for I/O TLB Writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CMD_TLB_PURGE 33 /* IO_COMMAND to Purge I/O TLB entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct ioa_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Runway Supervisory Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int32_t unused1[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) uint32_t io_command; /* Offset 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) uint32_t io_status; /* Offset 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) uint32_t io_control; /* Offset 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int32_t unused2[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Runway Auxiliary Register Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) uint32_t io_err_resp; /* Offset 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) uint32_t io_err_info; /* Offset 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) uint32_t io_err_req; /* Offset 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) uint32_t io_err_resp_hi; /* Offset 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) uint32_t io_tlb_entry_m; /* Offset 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) uint32_t io_tlb_entry_l; /* Offset 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) uint32_t unused3[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) uint32_t io_pdir_base; /* Offset 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) uint32_t io_io_low_hv; /* Offset 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) uint32_t io_io_high_hv; /* Offset 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) uint32_t unused4[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) uint32_t io_chain_id_mask; /* Offset 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) uint32_t unused5[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) uint32_t io_io_low; /* Offset 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) uint32_t io_io_high; /* Offset 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ** IOA Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ** -------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ** Runway IO_CONTROL Register (+0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ** The Runway IO_CONTROL register controls the forwarding of transactions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ** | 0 ... 13 | 14 15 | 16 ... 21 | 22 | 23 24 | 25 ... 31 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ** | HV | TLB | reserved | HV | mode | reserved |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ** o mode field indicates the address translation of transactions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ** forwarded from Runway to GSC+:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ** Mode Name Value Definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ** Off (default) 0 Opaque to matching addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ** Include 1 Transparent for matching addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ** Peek 3 Map matching addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ** + "Off" mode: Runway transactions which match the I/O range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ** specified by the IO_IO_LOW/IO_IO_HIGH registers will be ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ** + "Include" mode: all addresses within the I/O range specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ** by the IO_IO_LOW and IO_IO_HIGH registers are transparently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ** forwarded. This is the I/O Adapter's normal operating mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ** + "Peek" mode: used during system configuration to initialize the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ** GSC+ bus. Runway Write_Shorts in the address range specified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ** IO_IO_LOW and IO_IO_HIGH are forwarded through the I/O Adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ** *AND* the GSC+ address is remapped to the Broadcast Physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ** Address space by setting the 14 high order address bits of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ** 32 bit GSC+ address to ones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ** o TLB field affects transactions which are forwarded from GSC+ to Runway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ** "Real" mode is the poweron default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ** TLB Mode Value Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ** Real 0 No TLB translation. Address is directly mapped and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ** virtual address is composed of selected physical bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ** Error 1 Software fills the TLB manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ** Normal 2 IOA fetches IO TLB misses from IO PDIR (in host memory).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ** IO_IO_LOW_HV +0x60 (HV dependent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ** IO_IO_HIGH_HV +0x64 (HV dependent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ** IO_IO_LOW +0x78 (Architected register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ** IO_IO_HIGH +0x7c (Architected register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ** IO_IO_LOW and IO_IO_HIGH set the lower and upper bounds of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ** I/O Adapter address space, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ** 0 ... 7 | 8 ... 15 | 16 ... 31 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ** 11111111 | 11111111 | address |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ** Each LOW/HIGH pair describes a disjoint address space region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ** (2 per GSC+ port). Each incoming Runway transaction address is compared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ** with both sets of LOW/HIGH registers. If the address is in the range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ** greater than or equal to IO_IO_LOW and less than IO_IO_HIGH the transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ** for forwarded to the respective GSC+ bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ** Specify IO_IO_LOW equal to or greater than IO_IO_HIGH to avoid specifying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ** an address space region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ** In order for a Runway address to reside within GSC+ extended address space:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ** Runway Address [0:7] must identically compare to 8'b11111111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ** Runway Address [8:11] must be equal to IO_IO_LOW(_HV)[16:19]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ** Runway Address [12:23] must be greater than or equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ** IO_IO_LOW(_HV)[20:31] and less than IO_IO_HIGH(_HV)[20:31].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ** Runway Address [24:39] is not used in the comparison.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ** When the Runway transaction is forwarded to GSC+, the GSC+ address is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ** as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ** GSC+ Address[0:3] 4'b1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ** GSC+ Address[4:29] Runway Address[12:37]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ** GSC+ Address[30:31] 2'b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ** All 4 Low/High registers must be initialized (by PDC) once the lower bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ** is interrogated and address space is defined. The operating system will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ** modify the architectural IO_IO_LOW and IO_IO_HIGH registers following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ** the PDC initialization. However, the hardware version dependent IO_IO_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ** and IO_IO_HIGH registers should not be subsequently altered by the OS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ** Writes to both sets of registers will take effect immediately, bypassing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ** the queues, which ensures that subsequent Runway transactions are checked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ** against the updated bounds values. However reads are queued, introducing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ** the possibility of a read being bypassed by a subsequent write to the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ** register. This sequence can be avoided by having software wait for read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ** returns before issuing subsequent writes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct ioc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct ioa_registers __iomem *ioc_regs; /* I/O MMU base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 *res_map; /* resource map, bit == pdir entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u64 *pdir_base; /* physical base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 pdir_size; /* bytes, function of IOV Space size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 res_hint; /* next available IOVP -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) circular search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 res_size; /* size of resource map in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) spinlock_t res_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CCIO_SEARCH_SAMPLE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned long avg_search[CCIO_SEARCH_SAMPLE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long avg_idx; /* current index into avg_search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long used_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long msingle_calls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned long msingle_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned long msg_calls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long msg_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned long usingle_calls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long usingle_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned long usg_calls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned long usg_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned short cujo20_bug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* STUFF We don't need in performance path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 chainid_shift; /* specify bit location of chain_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct ioc *next; /* Linked list of discovered iocs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) const char *name; /* device name from firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int hw_path; /* the hardware path this ioc is associatd with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct pci_dev *fake_pci_dev; /* the fake pci_dev for non-pci devs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct resource mmio_region[2]; /* The "routed" MMIO regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static struct ioc *ioc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int ioc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /**************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * I/O Pdir Resource Management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Bits set in the resource map are in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Each bit can represent a number of pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * LSbs represent lower addresses (IOVA's).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * This was was copied from sba_iommu.c. Don't try to unify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * the two resource managers unless a way to have different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * allocation policies is also adjusted. We'd like to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * I/O TLB thrashing by having resource allocation policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * match the I/O TLB replacement policy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ***************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IOVP_SIZE PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IOVP_SHIFT PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IOVP_MASK PAGE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Convert from IOVP to IOVA and vice versa. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CCIO_IOVA(iovp,offset) ((iovp) | (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CCIO_IOVP(iova) ((iova) & IOVP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MKIOVP(pdir_idx) ((long)(pdir_idx) << IOVP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MKIOVA(iovp,offset) (dma_addr_t)((long)iovp | (long)offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ** Don't worry about the 150% average search length on a miss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ** If the search wraps around, and passes the res_hint, it will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ** cause the kernel to panic anyhow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CCIO_SEARCH_LOOP(ioc, res_idx, mask, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) for(; res_ptr < res_end; ++res_ptr) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int ret;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int idx;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) idx = (unsigned int)((unsigned long)res_ptr - (unsigned long)ioc->res_map); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ret = iommu_is_span_boundary(idx << 3, pages_needed, 0, boundary_size);\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if ((0 == (*res_ptr & mask)) && !ret) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *res_ptr |= mask; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) res_idx = idx;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ioc->res_hint = res_idx + (size >> 3); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) goto resource_found; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CCIO_FIND_FREE_MAPPING(ioa, res_idx, mask, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u##size *res_ptr = (u##size *)&((ioc)->res_map[ioa->res_hint & ~((size >> 3) - 1)]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u##size *res_end = (u##size *)&(ioc)->res_map[ioa->res_size]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) CCIO_SEARCH_LOOP(ioc, res_idx, mask, size); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) res_ptr = (u##size *)&(ioc)->res_map[0]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) CCIO_SEARCH_LOOP(ioa, res_idx, mask, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ** Find available bit in this ioa's resource map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ** Use a "circular" search:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ** o Most IOVA's are "temporary" - avg search time should be small.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ** o keep a history of what happened for debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ** o KISS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ** Perf optimizations:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ** o search for log2(size) bits at a time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ** o search for available resource bits using byte/word/whatever.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ** o use different search for "large" (eg > 4 pages) or "very large"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ** (eg > 16 pages) mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * ccio_alloc_range - Allocate pages in the ioc's resource map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * @ioc: The I/O Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * @pages_needed: The requested number of pages to be mapped into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * I/O Pdir...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * This function searches the resource map of the ioc to locate a range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * of available pages for the requested size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ccio_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int pages_needed = size >> IOVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int res_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long boundary_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) unsigned long cr_start = mfctl(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) BUG_ON(pages_needed == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) BUG_ON((pages_needed * IOVP_SIZE) > DMA_CHUNK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DBG_RES("%s() size: %d pages_needed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) __func__, size, pages_needed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ** "seek and ye shall find"...praying never hurts either...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ** ggg sacrifices another 710 to the computer gods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) boundary_size = dma_get_seg_boundary_nr_pages(dev, IOVP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (pages_needed <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * LAN traffic will not thrash the TLB IFF the same NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * uses 8 adjacent pages to map separate payload data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * ie the same byte in the resource bit map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* FIXME: bit search should shift it's way through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * an unsigned long - not byte at a time. As it is now,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * we effectively allocate this byte to this mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned long mask = ~(~0UL >> pages_needed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CCIO_FIND_FREE_MAPPING(ioc, res_idx, mask, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xff, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) } else if (pages_needed <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) CCIO_FIND_FREE_MAPPING(ioc, res_idx, 0xffff, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) } else if (pages_needed <= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~(unsigned int)0, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #ifdef __LP64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else if (pages_needed <= 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) CCIO_FIND_FREE_MAPPING(ioc, res_idx, ~0UL, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) panic("%s: %s() Too many pages to map. pages_needed: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) __FILE__, __func__, pages_needed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) panic("%s: %s() I/O MMU is out of mapping resources.\n", __FILE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) resource_found:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DBG_RES("%s() res_idx %d res_hint: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __func__, res_idx, ioc->res_hint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned long cr_end = mfctl(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned long tmp = cr_end - cr_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* check for roll over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ioc->avg_search[ioc->avg_idx++] = cr_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ioc->avg_idx &= CCIO_SEARCH_SAMPLE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ioc->used_pages += pages_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ** return the bit address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return res_idx << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CCIO_FREE_MAPPINGS(ioc, res_idx, mask, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u##size *res_ptr = (u##size *)&((ioc)->res_map[res_idx]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) BUG_ON((*res_ptr & mask) != mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *res_ptr &= ~(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * ccio_free_range - Free pages from the ioc's resource map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * @ioc: The I/O Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * @iova: The I/O Virtual Address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * @pages_mapped: The requested number of pages to be freed from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * I/O Pdir.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * This function frees the resouces allocated for the iova.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ccio_free_range(struct ioc *ioc, dma_addr_t iova, unsigned long pages_mapped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned long iovp = CCIO_IOVP(iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int res_idx = PDIR_INDEX(iovp) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) BUG_ON(pages_mapped == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) BUG_ON((pages_mapped * IOVP_SIZE) > DMA_CHUNK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) BUG_ON(pages_mapped > BITS_PER_LONG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) DBG_RES("%s(): res_idx: %d pages_mapped %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) __func__, res_idx, pages_mapped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ioc->used_pages -= pages_mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if(pages_mapped <= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* see matching comments in alloc_range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned long mask = ~(~0UL >> pages_mapped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) CCIO_FREE_MAPPINGS(ioc, res_idx, mask, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffUL, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } else if(pages_mapped <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) CCIO_FREE_MAPPINGS(ioc, res_idx, 0xffffUL, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } else if(pages_mapped <= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) CCIO_FREE_MAPPINGS(ioc, res_idx, ~(unsigned int)0, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #ifdef __LP64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) } else if(pages_mapped <= 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) CCIO_FREE_MAPPINGS(ioc, res_idx, ~0UL, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) panic("%s:%s() Too many pages to unmap.\n", __FILE__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /****************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ** CCIO dma_ops support routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) *****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) typedef unsigned long space_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define KERNEL_SPACE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ** DMA "Page Type" and Hints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ** o if SAFE_DMA isn't set, mapping is for FAST_DMA. SAFE_DMA should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ** set for subcacheline DMA transfers since we don't want to damage the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ** other part of a cacheline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ** o SAFE_DMA must be set for "memory" allocated via pci_alloc_consistent().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ** This bit tells U2 to do R/M/W for partial cachelines. "Streaming"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ** data can avoid this if the mapping covers full cache lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ** o STOP_MOST is needed for atomicity across cachelines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ** Apparently only "some EISA devices" need this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ** to use this hint iff the EISA devices needs this feature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ** According to the U2 ERS, STOP_MOST enabled pages hurt performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ** o PREFETCH should *not* be set for cases like Multiple PCI devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ** behind GSCtoPCI (dino) bus converter. Only one cacheline per GSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ** device can be fetched and multiply DMA streams will thrash the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ** prefetch buffer and burn memory bandwidth. See 6.7.3 "Prefetch Rules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ** and Invalidation of Prefetch Entries".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ** FIXME: the default hints need to be per GSC device - not global.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ** HP-UX dorks: linux device driver programming model is totally different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ** than HP-UX's. HP-UX always sets HINT_PREFETCH since it's drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ** do special things to work on non-coherent platforms...linux has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ** be much more careful with this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define IOPDIR_VALID 0x01UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define HINT_SAFE_DMA 0x02UL /* used for pci_alloc_consistent() pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #ifdef CONFIG_EISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define HINT_STOP_MOST 0x04UL /* LSL support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define HINT_STOP_MOST 0x00UL /* only needed for "some EISA devices" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define HINT_UDPATE_ENB 0x08UL /* not used/supported by U2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define HINT_PREFETCH 0x10UL /* for outbound pages which are not SAFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ** Use direction (ie PCI_DMA_TODEVICE) to pick hint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ** ccio_alloc_consistent() depends on this to get SAFE_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ** when it passes in BIDIRECTIONAL flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static u32 hint_lookup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) [PCI_DMA_BIDIRECTIONAL] = HINT_STOP_MOST | HINT_SAFE_DMA | IOPDIR_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) [PCI_DMA_TODEVICE] = HINT_STOP_MOST | HINT_PREFETCH | IOPDIR_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) [PCI_DMA_FROMDEVICE] = HINT_STOP_MOST | IOPDIR_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * ccio_io_pdir_entry - Initialize an I/O Pdir.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * @pdir_ptr: A pointer into I/O Pdir.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * @sid: The Space Identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * @vba: The virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * @hints: The DMA Hint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * Given a virtual address (vba, arg2) and space id, (sid, arg1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * load the I/O PDIR entry pointed to by pdir_ptr (arg0). Each IO Pdir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * entry consists of 8 bytes as shown below (MSB == bit 0):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * WORD 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * +------+----------------+-----------------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * | Phys | Virtual Index | Phys |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * | 0:3 | 0:11 | 4:19 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * |4 bits| 12 bits | 16 bits |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * +------+----------------+-----------------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * WORD 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * +-----------------------+-----------------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * | Phys | Rsvd | Prefetch |Update |Rsvd |Lock |Safe |Valid |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * | 20:39 | | Enable |Enable | |Enable|DMA | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * | 20 bits | 5 bits | 1 bit |1 bit |2 bits|1 bit |1 bit |1 bit |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * +-----------------------+-----------------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * The virtual index field is filled with the results of the LCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * (Load Coherence Index) instruction. The 8 bits used for the virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * index are bits 12:19 of the value returned by LCI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static void CCIO_INLINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ccio_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned long hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) register unsigned long pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) register unsigned long ci; /* coherent index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* We currently only support kernel addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) BUG_ON(sid != KERNEL_SPACE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ** WORD 1 - low order word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ** "hints" parm includes the VALID bit!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ** "dep" clobbers the physical address offset bits as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pa = lpa(vba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) asm volatile("depw %1,31,12,%0" : "+r" (pa) : "r" (hints));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ((u32 *)pdir_ptr)[1] = (u32) pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ** WORD 0 - high order word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #ifdef __LP64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ** get bits 12:15 of physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ** shift bits 16:31 of physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ** and deposit them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) asm volatile ("extrd,u %1,15,4,%0" : "=r" (ci) : "r" (pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) asm volatile ("extrd,u %1,31,16,%0" : "+r" (pa) : "r" (pa));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) asm volatile ("depd %1,35,4,%0" : "+r" (pa) : "r" (ci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pa = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ** get CPU coherency index bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ** Grab virtual index [0:11]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ** Deposit virt_idx bits into I/O PDIR word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) asm volatile ("lci %%r0(%1), %0" : "=r" (ci) : "r" (vba));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) asm volatile ("extru %1,19,12,%0" : "+r" (ci) : "r" (ci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) asm volatile ("depw %1,15,12,%0" : "+r" (pa) : "r" (ci));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ((u32 *)pdir_ptr)[0] = (u32) pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ** PCX-U/U+ do. (eg C200/C240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ** PCX-T'? Don't know. (eg C110 or similar K-class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ** "Since PCX-U employs an offset hash that is incompatible with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ** the real mode coherence index generation of U2, the PDIR entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ** must be flushed to memory to retain coherence."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) asm_io_fdc(pdir_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) asm_io_sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * ccio_clear_io_tlb - Remove stale entries from the I/O TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * @ioc: The I/O Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * @iovp: The I/O Virtual Page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * Purge invalid I/O PDIR entries from the I/O TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * FIXME: Can we change the byte_cnt to pages_mapped?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static CCIO_INLINE void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ccio_clear_io_tlb(struct ioc *ioc, dma_addr_t iovp, size_t byte_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 chain_size = 1 << ioc->chainid_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) iovp &= IOVP_MASK; /* clear offset bits, just want pagenum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) byte_cnt += chain_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) while(byte_cnt > chain_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) WRITE_U32(CMD_TLB_PURGE | iovp, &ioc->ioc_regs->io_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) iovp += chain_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) byte_cnt -= chain_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * ccio_mark_invalid - Mark the I/O Pdir entries invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * @ioc: The I/O Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * @iova: The I/O Virtual Address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * @byte_cnt: The requested number of bytes to be freed from the I/O Pdir.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * Mark the I/O Pdir entries invalid and blow away the corresponding I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * TLB entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * FIXME: at some threshold it might be "cheaper" to just blow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * away the entire I/O TLB instead of individual entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * FIXME: Uturn has 256 TLB entries. We don't need to purge every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * PDIR entry - just once for each possible TLB entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * (We do need to maker I/O PDIR entries invalid regardless).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * FIXME: Can we change byte_cnt to pages_mapped?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static CCIO_INLINE void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ccio_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u32 iovp = (u32)CCIO_IOVP(iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) size_t saved_byte_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* round up to nearest page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) saved_byte_cnt = byte_cnt = ALIGN(byte_cnt, IOVP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) while(byte_cnt > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* invalidate one page at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned int idx = PDIR_INDEX(iovp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) char *pdir_ptr = (char *) &(ioc->pdir_base[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) BUG_ON(idx >= (ioc->pdir_size / sizeof(u64)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pdir_ptr[7] = 0; /* clear only VALID bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ** FIXME: PCX_W platforms don't need FDC/SYNC. (eg C360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ** PCX-U/U+ do. (eg C200/C240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ** See PDC_MODEL/option 0/SW_CAP for "Non-coherent IO-PDIR bit".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) asm_io_fdc(pdir_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) iovp += IOVP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) byte_cnt -= IOVP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) asm_io_sync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ccio_clear_io_tlb(ioc, CCIO_IOVP(iova), saved_byte_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /****************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ** CCIO dma_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) *****************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * ccio_dma_supported - Verify the IOMMU supports the DMA address range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * @dev: The PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * @mask: A bit mask describing the DMA address range of the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ccio_dma_supported(struct device *dev, u64 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if(dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* only support 32-bit or better devices (ie PCI/GSC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return (int)(mask >= 0xffffffffUL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * ccio_map_single - Map an address range into the IOMMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * @dev: The PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * @addr: The start address of the DMA region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * @size: The length of the DMA region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * @direction: The direction of the DMA transaction (to/from device).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * This function implements the pci_map_single function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static dma_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ccio_map_single(struct device *dev, void *addr, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) enum dma_data_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct ioc *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dma_addr_t iovp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dma_addr_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u64 *pdir_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned long hint = hint_lookup[(int)direction];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) BUG_ON(!dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ioc = GET_IOC(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (!ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return DMA_MAPPING_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) BUG_ON(size <= 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* save offset bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) offset = ((unsigned long) addr) & ~IOVP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* round up to nearest IOVP_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) size = ALIGN(size + offset, IOVP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) spin_lock_irqsave(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ioc->msingle_calls++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ioc->msingle_pages += size >> IOVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) idx = ccio_alloc_range(ioc, dev, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) iovp = (dma_addr_t)MKIOVP(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pdir_start = &(ioc->pdir_base[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) DBG_RUN("%s() 0x%p -> 0x%lx size: %0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) __func__, addr, (long)iovp | offset, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* If not cacheline aligned, force SAFE_DMA on the whole mess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if((size % L1_CACHE_BYTES) || ((unsigned long)addr % L1_CACHE_BYTES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) hint |= HINT_SAFE_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) while(size > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ccio_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long)addr, hint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) DBG_RUN(" pdir %p %08x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) pdir_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) (u32) (((u32 *) pdir_start)[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) (u32) (((u32 *) pdir_start)[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ++pdir_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) addr += IOVP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) size -= IOVP_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) spin_unlock_irqrestore(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* form complete address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return CCIO_IOVA(iovp, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static dma_addr_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ccio_map_page(struct device *dev, struct page *page, unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) size_t size, enum dma_data_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return ccio_map_single(dev, page_address(page) + offset, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * ccio_unmap_page - Unmap an address range from the IOMMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * @dev: The PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * @addr: The start address of the DMA region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * @size: The length of the DMA region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * @direction: The direction of the DMA transaction (to/from device).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ccio_unmap_page(struct device *dev, dma_addr_t iova, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) enum dma_data_direction direction, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct ioc *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dma_addr_t offset = iova & ~IOVP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) BUG_ON(!dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ioc = GET_IOC(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) WARN_ON(!ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) DBG_RUN("%s() iovp 0x%lx/%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) __func__, (long)iova, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) iova ^= offset; /* clear offset bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) size += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) size = ALIGN(size, IOVP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) spin_lock_irqsave(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ioc->usingle_calls++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ioc->usingle_pages += size >> IOVP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ccio_mark_invalid(ioc, iova, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ccio_free_range(ioc, iova, (size >> IOVP_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) spin_unlock_irqrestore(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * ccio_alloc - Allocate a consistent DMA mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * @dev: The PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * @size: The length of the DMA region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * @dma_handle: The DMA address handed back to the device (not the cpu).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * This function implements the pci_alloc_consistent function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static void *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ccio_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) void *ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* GRANT Need to establish hierarchy for non-PCI devs as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ** and then provide matching gsc_map_xxx() functions for them as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if(!hwdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* only support PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) *dma_handle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ret = (void *) __get_free_pages(flag, get_order(size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) memset(ret, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) *dma_handle = ccio_map_single(dev, ret, size, PCI_DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * ccio_free - Free a consistent DMA mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * @dev: The PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * @size: The length of the DMA region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * @cpu_addr: The cpu address returned from the ccio_alloc_consistent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * @dma_handle: The device address returned from the ccio_alloc_consistent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * This function implements the pci_free_consistent function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ccio_free(struct device *dev, size_t size, void *cpu_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dma_addr_t dma_handle, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ccio_unmap_page(dev, dma_handle, size, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) free_pages((unsigned long)cpu_addr, get_order(size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ** Since 0 is a valid pdir_base index value, can't use that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ** to determine if a value is valid or not. Use a flag to indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ** the SG list entry contains a valid pdir index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define PIDE_FLAG 0x80000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define IOMMU_MAP_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #include "iommu-helpers.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * ccio_map_sg - Map the scatter/gather list into the IOMMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * @dev: The PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * @sglist: The scatter/gather list to be mapped in the IOMMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * @nents: The number of entries in the scatter/gather list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * @direction: The direction of the DMA transaction (to/from device).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * This function implements the pci_map_sg function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ccio_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) enum dma_data_direction direction, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct ioc *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) int coalesced, filled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) unsigned long hint = hint_lookup[(int)direction];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) unsigned long prev_len = 0, current_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) BUG_ON(!dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ioc = GET_IOC(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* Fast path single entry scatterlists. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (nents == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) sg_dma_address(sglist) = ccio_map_single(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) sg_virt(sglist), sglist->length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) sg_dma_len(sglist) = sglist->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) for(i = 0; i < nents; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) prev_len += sglist[i].length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) spin_lock_irqsave(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ioc->msg_calls++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ** First coalesce the chunks and allocate I/O pdir space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ** If this is one DMA stream, we can properly map using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ** correct virtual address associated with each DMA page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ** w/o this association, we wouldn't have coherent DMA!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ** Access to the virtual address is what forces a two pass algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, ccio_alloc_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ** Program the I/O Pdir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ** map the virtual addresses to the I/O Pdir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ** o dma_address will contain the pdir index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ** o dma_len will contain the number of bytes to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ** o page/offset contain the virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) filled = iommu_fill_pdir(ioc, sglist, nents, hint, ccio_io_pdir_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) spin_unlock_irqrestore(&ioc->res_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) BUG_ON(coalesced != filled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) for (i = 0; i < filled; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) current_len += sg_dma_len(sglist + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) BUG_ON(current_len != prev_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return filled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * ccio_unmap_sg - Unmap the scatter/gather list from the IOMMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * @dev: The PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) * @sglist: The scatter/gather list to be unmapped from the IOMMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * @nents: The number of entries in the scatter/gather list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * @direction: The direction of the DMA transaction (to/from device).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * This function implements the pci_unmap_sg function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ccio_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) enum dma_data_direction direction, unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct ioc *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) BUG_ON(!dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ioc = GET_IOC(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (!ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) WARN_ON(!ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) DBG_RUN_SG("%s() START %d entries, %p,%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) __func__, nents, sg_virt(sglist), sglist->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ioc->usg_calls++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) while (nents && sg_dma_len(sglist)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ioc->usg_pages += sg_dma_len(sglist) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ccio_unmap_page(dev, sg_dma_address(sglist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) sg_dma_len(sglist), direction, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ++sglist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) nents--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static const struct dma_map_ops ccio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .dma_supported = ccio_dma_supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .alloc = ccio_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .free = ccio_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .map_page = ccio_map_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .unmap_page = ccio_unmap_page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .map_sg = ccio_map_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .unmap_sg = ccio_unmap_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .get_sgtable = dma_common_get_sgtable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .alloc_pages = dma_common_alloc_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .free_pages = dma_common_free_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int ccio_proc_info(struct seq_file *m, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct ioc *ioc = ioc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) while (ioc != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) unsigned int total_pages = ioc->res_size << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) unsigned long avg = 0, min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) seq_printf(m, "%s\n", ioc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) seq_printf(m, "Cujo 2.0 bug : %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) (ioc->cujo20_bug ? "yes" : "no"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) total_pages * 8, total_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) total_pages - ioc->used_pages, ioc->used_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) (int)(ioc->used_pages * 100 / total_pages));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ioc->res_size, total_pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #ifdef CCIO_COLLECT_STATS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) min = max = ioc->avg_search[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) for(j = 0; j < CCIO_SEARCH_SAMPLE; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) avg += ioc->avg_search[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if(ioc->avg_search[j] > max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) max = ioc->avg_search[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if(ioc->avg_search[j] < min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) min = ioc->avg_search[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) avg /= CCIO_SEARCH_SAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) min, avg, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) seq_printf(m, "pci_map_single(): %8ld calls %8ld pages (avg %d/1000)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ioc->msingle_calls, ioc->msingle_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* KLUGE - unmap_sg calls unmap_page for each mapped page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) min = ioc->usingle_calls - ioc->usg_calls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) max = ioc->usingle_pages - ioc->usg_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) seq_printf(m, "pci_unmap_single: %8ld calls %8ld pages (avg %d/1000)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) min, max, (int)((max * 1000)/min));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) seq_printf(m, "pci_map_sg() : %8ld calls %8ld pages (avg %d/1000)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ioc->msg_calls, ioc->msg_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) seq_printf(m, "pci_unmap_sg() : %8ld calls %8ld pages (avg %d/1000)\n\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ioc->usg_calls, ioc->usg_pages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #endif /* CCIO_COLLECT_STATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ioc = ioc->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int ccio_proc_bitmap_info(struct seq_file *m, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct ioc *ioc = ioc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) while (ioc != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ioc->res_size, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) seq_putc(m, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ioc = ioc->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) break; /* XXX - remove me */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #endif /* CONFIG_PROC_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * ccio_find_ioc - Find the ioc in the ioc_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * @hw_path: The hardware path of the ioc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * This function searches the ioc_list for an ioc that matches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * the provide hardware path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static struct ioc * ccio_find_ioc(int hw_path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct ioc *ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ioc = ioc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) for (i = 0; i < ioc_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (ioc->hw_path == hw_path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ioc = ioc->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * ccio_get_iommu - Find the iommu which controls this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * @dev: The parisc device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * This function searches through the registered IOMMU's and returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * the appropriate IOMMU for the device based on its hardware path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) void * ccio_get_iommu(const struct parisc_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dev = find_pa_parent_type(dev, HPHW_IOA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return ccio_find_ioc(dev->hw_path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define CUJO_20_STEP 0x10000000 /* inc upper nibble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Cujo 2.0 has a bug which will silently corrupt data being transferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * to/from certain pages. To avoid this happening, we mark these pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * as `used', and ensure that nothing will try to allocate from them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) void __init ccio_cujo20_fixup(struct parisc_device *cujo, u32 iovp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct parisc_device *dev = parisc_parent(cujo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct ioc *ioc = ccio_get_iommu(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) u8 *res_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ioc->cujo20_bug = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) res_ptr = ioc->res_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) idx = PDIR_INDEX(iovp) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) while (idx < ioc->res_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) res_ptr[idx] |= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) idx += PDIR_INDEX(CUJO_20_STEP) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* GRANT - is this needed for U2 or not? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ** Get the size of the I/O TLB for this I/O MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ** If spa_shift is non-zero (ie probably U2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ** then calculate the I/O TLB size using spa_shift.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ** Otherwise we are supposed to get the IODC entry point ENTRY TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ** and execute it. However, both U2 and Uturn firmware supplies spa_shift.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ** I think only Java (K/D/R-class too?) systems don't do this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ccio_get_iotlb_size(struct parisc_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (dev->spa_shift == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) panic("%s() : Can't determine I/O TLB size.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return (1 << dev->spa_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* Uturn supports 256 TLB entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define CCIO_CHAINID_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define CCIO_CHAINID_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #endif /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* We *can't* support JAVA (T600). Venture there at your own risk. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static const struct parisc_device_id ccio_tbl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) { HPHW_IOA, HVERSION_REV_ANY_ID, U2_IOA_RUNWAY, 0xb }, /* U2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) { HPHW_IOA, HVERSION_REV_ANY_ID, UTURN_IOA_RUNWAY, 0xb }, /* UTurn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static int ccio_probe(struct parisc_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static struct parisc_driver ccio_driver __refdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .name = "ccio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .id_table = ccio_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .probe = ccio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * ccio_ioc_init - Initialize the I/O Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * @ioc: The I/O Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) * Initialize the I/O Controller which includes setting up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * I/O Page Directory, the resource map, and initalizing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * U2/Uturn chip into virtual mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ccio_ioc_init(struct ioc *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) unsigned int iov_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u32 iova_space_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) ** Determine IOVA Space size from memory size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ** Ideally, PCI drivers would register the maximum number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ** of DMA they can have outstanding for each device they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ** own. Next best thing would be to guess how much DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ** can be outstanding based on PCI Class/sub-class. Both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ** methods still require some "extra" to support PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) iova_space_size = (u32) (totalram_pages() / count_parisc_driver(&ccio_driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* limit IOVA space size to 1MB-1GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) iova_space_size = 1 << (20 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #ifdef __LP64__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) } else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) iova_space_size = 1 << (30 - PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ** iova space must be log2() in size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ** thus, pdir/res_map will also be log2().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* We could use larger page sizes in order to *decrease* the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) ** of mappings needed. (ie 8k pages means 1/2 the mappings).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ** Note: Grant Grunder says "Using 8k I/O pages isn't trivial either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) ** since the pages must also be physically contiguous - typically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) ** this is the case under linux."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) iov_order = get_order(iova_space_size << PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /* iova_space_size is now bytes, not pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) iova_space_size = 1 << (iov_order + PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) BUG_ON(ioc->pdir_size > 8 * 1024 * 1024); /* max pdir size <= 8MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* Verify it's a power of two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) BUG_ON((1 << get_order(ioc->pdir_size)) != (ioc->pdir_size >> PAGE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) DBG_INIT("%s() hpa 0x%p mem %luMB IOV %dMB (%d bits)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) __func__, ioc->ioc_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) (unsigned long) totalram_pages() >> (20 - PAGE_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) iova_space_size>>20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) iov_order + PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) ioc->pdir_base = (u64 *)__get_free_pages(GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) get_order(ioc->pdir_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if(NULL == ioc->pdir_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) panic("%s() could not allocate I/O Page Table\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) memset(ioc->pdir_base, 0, ioc->pdir_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) BUG_ON((((unsigned long)ioc->pdir_base) & PAGE_MASK) != (unsigned long)ioc->pdir_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) DBG_INIT(" base %p\n", ioc->pdir_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* resource map size dictated by pdir_size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) ioc->res_size = (ioc->pdir_size / sizeof(u64)) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) DBG_INIT("%s() res_size 0x%x\n", __func__, ioc->res_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) ioc->res_map = (u8 *)__get_free_pages(GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) get_order(ioc->res_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if(NULL == ioc->res_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) panic("%s() could not allocate resource map\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) memset(ioc->res_map, 0, ioc->res_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /* Initialize the res_hint to 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ioc->res_hint = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* Initialize the spinlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) spin_lock_init(&ioc->res_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ** Chainid is the upper most bits of an IOVP used to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) ** which TLB entry an IOVP will use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ioc->chainid_shift = get_order(iova_space_size) + PAGE_SHIFT - CCIO_CHAINID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) DBG_INIT(" chainid_shift 0x%x\n", ioc->chainid_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ** Initialize IOA hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) WRITE_U32(CCIO_CHAINID_MASK << ioc->chainid_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) &ioc->ioc_regs->io_chain_id_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) WRITE_U32(virt_to_phys(ioc->pdir_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &ioc->ioc_regs->io_pdir_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ** Go to "Virtual Mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) WRITE_U32(IOA_NORMAL_MODE, &ioc->ioc_regs->io_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ** Initialize all I/O TLB entries to 0 (Valid bit off).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) WRITE_U32(0, &ioc->ioc_regs->io_tlb_entry_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) for(i = 1 << CCIO_CHAINID_SHIFT; i ; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) WRITE_U32((CMD_TLB_DIRECT_WRITE | (i << ioc->chainid_shift)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) &ioc->ioc_regs->io_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ccio_init_resource(struct resource *res, char *name, void __iomem *ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) res->parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) res->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * bracing ((signed) ...) are required for 64bit kernel because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * we only want to sign extend the lower 16 bits of the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * The upper 16-bits of range registers are hardcoded to 0xffff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) res->start = (unsigned long)((signed) READ_U32(ioaddr) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) res->end = (unsigned long)((signed) (READ_U32(ioaddr + 4) << 16) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) res->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * Check if this MMIO range is disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (res->end + 1 == res->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* On some platforms (e.g. K-Class), we have already registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * resources for devices reported by firmware. Some are children
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * of ccio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * "insert" ccio ranges in the mmio hierarchy (/proc/iomem).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) result = insert_resource(&iomem_resource, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) printk(KERN_ERR "%s() failed to claim CCIO bus address space (%08lx,%08lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) __func__, (unsigned long)res->start, (unsigned long)res->end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static void __init ccio_init_resources(struct ioc *ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct resource *res = ioc->mmio_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) char *name = kmalloc(14, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) snprintf(name, 14, "GSC Bus [%d/]", ioc->hw_path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ccio_init_resource(res, name, &ioc->ioc_regs->io_io_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ccio_init_resource(res + 1, name, &ioc->ioc_regs->io_io_low_hv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static int new_ioc_area(struct resource *res, unsigned long size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) unsigned long min, unsigned long max, unsigned long align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (max <= min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) res->start = (max - size + 1) &~ (align - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) res->end = res->start + size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /* We might be trying to expand the MMIO range to include
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) * a child device that has already registered it's MMIO space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) * Use "insert" instead of request_resource().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (!insert_resource(&iomem_resource, res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return new_ioc_area(res, size, min, max - size, align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static int expand_ioc_area(struct resource *res, unsigned long size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) unsigned long min, unsigned long max, unsigned long align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) unsigned long start, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (!res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return new_ioc_area(res, size, min, max, align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) start = (res->start - size) &~ (align - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) len = res->end - start + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (start >= min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (!adjust_resource(res, start, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) len = ((size + res->end + align) &~ (align - 1)) - start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (start + len <= max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (!adjust_resource(res, start, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) * Dino calls this function. Beware that we may get called on systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) * which have no IOC (725, B180, C160L, etc) but do have a Dino.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) * So it's legal to find no parent IOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) * Some other issues: one of the resources in the ioc may be unassigned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) int ccio_allocate_resource(const struct parisc_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct resource *res, unsigned long size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) unsigned long min, unsigned long max, unsigned long align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) struct resource *parent = &iomem_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) struct ioc *ioc = ccio_get_iommu(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (!ioc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) parent = ioc->mmio_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (parent->parent &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) !allocate_resource(parent, res, size, min, max, align, NULL, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if ((parent + 1)->parent &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) !allocate_resource(parent + 1, res, size, min, max, align,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) NULL, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (!expand_ioc_area(parent, size, min, max, align)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) __raw_writel(((parent->start)>>16) | 0xffff0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) &ioc->ioc_regs->io_io_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) __raw_writel(((parent->end)>>16) | 0xffff0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) &ioc->ioc_regs->io_io_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) } else if (!expand_ioc_area(parent + 1, size, min, max, align)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) parent++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) __raw_writel(((parent->start)>>16) | 0xffff0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) &ioc->ioc_regs->io_io_low_hv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) __raw_writel(((parent->end)>>16) | 0xffff0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) &ioc->ioc_regs->io_io_high_hv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return allocate_resource(parent, res, size, min, max, align, NULL,NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) int ccio_request_resource(const struct parisc_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct resource *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct ioc *ioc = ccio_get_iommu(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (!ioc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) parent = &iomem_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) } else if ((ioc->mmio_region->start <= res->start) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) (res->end <= ioc->mmio_region->end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) parent = ioc->mmio_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) } else if (((ioc->mmio_region + 1)->start <= res->start) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) (res->end <= (ioc->mmio_region + 1)->end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) parent = ioc->mmio_region + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* "transparent" bus bridges need to register MMIO resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * firmware assigned them. e.g. children of hppb.c (e.g. K-class)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * registered their resources in the PDC "bus walk" (See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * arch/parisc/kernel/inventory.c).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return insert_resource(parent, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) * ccio_probe - Determine if ccio should claim this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) * @dev: The device which has been found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) * Determine if ccio should claim this chip (return 0) or not (return 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) * If so, initialize the chip and tell other partners in crime they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) * have work to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static int __init ccio_probe(struct parisc_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) struct ioc *ioc, **ioc_p = &ioc_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct pci_hba_data *hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ioc = kzalloc(sizeof(struct ioc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (ioc == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) printk(KERN_ERR MODULE_NAME ": memory allocation failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ioc->name = dev->id.hversion == U2_IOA_RUNWAY ? "U2" : "UTurn";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) printk(KERN_INFO "Found %s at 0x%lx\n", ioc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) (unsigned long)dev->hpa.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) for (i = 0; i < ioc_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ioc_p = &(*ioc_p)->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) *ioc_p = ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ioc->hw_path = dev->hw_path;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) ioc->ioc_regs = ioremap(dev->hpa.start, 4096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (!ioc->ioc_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) kfree(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ccio_ioc_init(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) ccio_init_resources(ioc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) hppa_dma_ops = &ccio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) hba = kzalloc(sizeof(*hba), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* if this fails, no I/O cards will work, so may as well bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) BUG_ON(hba == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) hba->iommu = ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) dev->dev.platform_data = hba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (ioc_count == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) proc_create_single(MODULE_NAME, 0, proc_runway_root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ccio_proc_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) proc_create_single(MODULE_NAME"-bitmap", 0, proc_runway_root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) ccio_proc_bitmap_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ioc_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) * ccio_init - ccio initialization procedure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) * Register this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) void __init ccio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) register_parisc_driver(&ccio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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