Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2019 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/firmware/xlnx-zynqmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SILICON_REVISION_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct zynqmp_nvmem_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static int zynqmp_nvmem_read(void *context, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			     void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	int idcode, version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct zynqmp_nvmem_data *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	ret = zynqmp_pm_get_chipid(&idcode, &version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	*(int *)val = version & SILICON_REVISION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static struct nvmem_config econfig = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	.name = "zynqmp-nvmem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	.word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	.size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	.read_only = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const struct of_device_id zynqmp_nvmem_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	{ .compatible = "xlnx,zynqmp-nvmem-fw", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MODULE_DEVICE_TABLE(of, zynqmp_nvmem_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int zynqmp_nvmem_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	struct zynqmp_nvmem_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	priv = devm_kzalloc(dev, sizeof(struct zynqmp_nvmem_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	econfig.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	econfig.reg_read = zynqmp_nvmem_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	econfig.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	priv->nvmem = devm_nvmem_register(dev, &econfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	return PTR_ERR_OR_ZERO(priv->nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct platform_driver zynqmp_nvmem_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	.probe = zynqmp_nvmem_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		.name = "zynqmp-nvmem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		.of_match_table = zynqmp_nvmem_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) module_platform_driver(zynqmp_nvmem_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>, Nava kishore Manne <navam@xilinx.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MODULE_DESCRIPTION("ZynqMP NVMEM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_LICENSE("GPL");