Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * STM32 Factory-programmed memory read access driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Fabrice Gasnier <fabrice.gasnier@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /* BSEC secure service access from non-secure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define STM32_SMC_BSEC			0x82001003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define STM32_SMC_READ_SHADOW		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define STM32_SMC_PROG_OTP		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define STM32_SMC_WRITE_SHADOW		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define STM32_SMC_READ_OTP		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* shadow registers offest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define STM32MP15_BSEC_DATA0		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* 32 (x 32-bits) lower shadow registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define STM32MP15_BSEC_NUM_LOWER	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) struct stm32_romem_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) struct stm32_romem_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct nvmem_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static int stm32_romem_read(void *context, unsigned int offset, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			    size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct stm32_romem_priv *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u8 *buf8 = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	for (i = offset; i < offset + bytes; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		*buf8++ = readb_relaxed(priv->base + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	if (res.a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		*result = (u32)res.a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static int stm32_bsec_read(void *context, unsigned int offset, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			   size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct stm32_romem_priv *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct device *dev = priv->cfg.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	u32 roffset, rbytes, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	u8 *buf8 = buf, *val8 = (u8 *)&val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	int i, j = 0, ret, skip_bytes, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	/* Round unaligned access to 32-bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	roffset = rounddown(offset, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	skip_bytes = offset & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	rbytes = roundup(bytes + skip_bytes, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (roffset + rbytes > priv->cfg.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	for (i = roffset; (i < roffset + rbytes); i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		u32 otp = i >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		if (otp < STM32MP15_BSEC_NUM_LOWER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			/* read lower data from shadow registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			val = readl_relaxed(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				priv->base + STM32MP15_BSEC_DATA0 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 					     &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 				dev_err(dev, "Can't read data%d (%d)\n", otp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 					ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		/* skip first bytes in case of unaligned read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		if (skip_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			size = min(bytes, (size_t)(4 - skip_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			size = min(bytes, (size_t)4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		memcpy(&buf8[j], &val8[skip_bytes], size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		bytes -= size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		j += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		skip_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int stm32_bsec_write(void *context, unsigned int offset, void *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			    size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct stm32_romem_priv *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct device *dev = priv->cfg.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u32 *buf32 = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* Allow only writing complete 32-bits aligned words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if ((bytes % 4) || (offset % 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	for (i = offset; i < offset + bytes; i += 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		ret = stm32_bsec_smc(STM32_SMC_PROG_OTP, i >> 2, *buf32++,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				     NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			dev_err(dev, "Can't write data%d (%d)\n", i >> 2, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int stm32_romem_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	const struct stm32_romem_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct stm32_romem_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	priv->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	priv->cfg.name = "stm32-romem";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	priv->cfg.word_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	priv->cfg.stride = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	priv->cfg.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	priv->cfg.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	priv->cfg.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	cfg = (const struct stm32_romem_cfg *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		of_match_device(dev->driver->of_match_table, dev)->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		priv->cfg.read_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		priv->cfg.size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		priv->cfg.reg_read = stm32_romem_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		priv->cfg.size = cfg->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		priv->cfg.reg_read = stm32_bsec_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		priv->cfg.reg_write = stm32_bsec_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.size = 384, /* 96 x 32-bits data words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct of_device_id stm32_romem_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	{ .compatible = "st,stm32f4-otp", }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.compatible = "st,stm32mp15-bsec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.data = (void *)&stm32mp15_bsec_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MODULE_DEVICE_TABLE(of, stm32_romem_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct platform_driver stm32_romem_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.probe = stm32_romem_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.name = "stm32-romem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.of_match_table = of_match_ptr(stm32_romem_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) module_platform_driver(stm32_romem_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MODULE_DESCRIPTION("STMicroelectronics STM32 RO-MEM");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MODULE_ALIAS("platform:nvmem-stm32-romem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MODULE_LICENSE("GPL v2");