^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2019 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/hwspinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SPRD_EFUSE_ENABLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SPRD_EFUSE_ERR_FLAG 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SPRD_EFUSE_ERR_CLR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SPRD_EFUSE_MAGIC_NUM 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPRD_EFUSE_FW_CFG 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPRD_EFUSE_PW_SWT 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPRD_EFUSE_MEM(val) (0x1000 + ((val) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPRD_EFUSE_VDD_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPRD_EFUSE_AUTO_CHECK_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPRD_EFUSE_DOUBLE_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPRD_EFUSE_MARGIN_RD_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPRD_EFUSE_LOCK_WR_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPRD_EFUSE_ERR_CLR_MASK GENMASK(13, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPRD_EFUSE_ENK1_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPRD_EFUSE_ENK2_ON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPRD_EFUSE_PROG_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPRD_EFUSE_MAGIC_NUMBER 0x8810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Block width (bytes) definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPRD_EFUSE_BLOCK_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * The Spreadtrum AP efuse contains 2 parts: normal efuse and secure efuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * and we can only access the normal efuse in kernel. So define the normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * block offset index and normal block numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPRD_EFUSE_NORMAL_BLOCK_NUMS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPRD_EFUSE_NORMAL_BLOCK_OFFSET 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Timeout (ms) for the trylock of hardware spinlocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPRD_EFUSE_HWLOCK_TIMEOUT 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Since different Spreadtrum SoC chip can have different normal block numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * and offset. And some SoC can support block double feature, which means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * when reading or writing data to efuse memory, the controller can save double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * data in case one data become incorrect after a long period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Thus we should save them in the device data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct sprd_efuse_variant_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 blk_nums;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 blk_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bool blk_double;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct sprd_efuse {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct hwspinlock *hwlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const struct sprd_efuse_variant_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static const struct sprd_efuse_variant_data ums312_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .blk_nums = SPRD_EFUSE_NORMAL_BLOCK_NUMS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .blk_offset = SPRD_EFUSE_NORMAL_BLOCK_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .blk_double = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * On Spreadtrum platform, we have multi-subsystems will access the unique
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * efuse controller, so we need one hardware spinlock to synchronize between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * the multiple subsystems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int sprd_efuse_lock(struct sprd_efuse *efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mutex_lock(&efuse->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret = hwspin_lock_timeout_raw(efuse->hwlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SPRD_EFUSE_HWLOCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev_err(efuse->dev, "timeout get the hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mutex_unlock(&efuse->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void sprd_efuse_unlock(struct sprd_efuse *efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) hwspin_unlock_raw(efuse->hwlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mutex_unlock(&efuse->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void sprd_efuse_set_prog_power(struct sprd_efuse *efuse, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val &= ~SPRD_EFUSE_ENK2_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val &= ~SPRD_EFUSE_ENK1_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Open or close efuse power need wait 1000us to make power stable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) usleep_range(1000, 1200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val |= SPRD_EFUSE_ENK1_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val |= SPRD_EFUSE_ENK2_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Open or close efuse power need wait 1000us to make power stable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) usleep_range(1000, 1200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void sprd_efuse_set_read_power(struct sprd_efuse *efuse, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) val |= SPRD_EFUSE_VDD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val &= ~SPRD_EFUSE_VDD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel(val, efuse->base + SPRD_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Open or close efuse power need wait 1000us to make power stable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) usleep_range(1000, 1200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void sprd_efuse_set_prog_lock(struct sprd_efuse *efuse, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) val |= SPRD_EFUSE_LOCK_WR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val &= ~SPRD_EFUSE_LOCK_WR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) writel(val, efuse->base + SPRD_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void sprd_efuse_set_auto_check(struct sprd_efuse *efuse, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val |= SPRD_EFUSE_AUTO_CHECK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) val &= ~SPRD_EFUSE_AUTO_CHECK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writel(val, efuse->base + SPRD_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void sprd_efuse_set_data_double(struct sprd_efuse *efuse, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) val |= SPRD_EFUSE_DOUBLE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) val &= ~SPRD_EFUSE_DOUBLE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writel(val, efuse->base + SPRD_EFUSE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void sprd_efuse_set_prog_en(struct sprd_efuse *efuse, bool en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val |= SPRD_EFUSE_PROG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) val &= ~SPRD_EFUSE_PROG_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel(val, efuse->base + SPRD_EFUSE_PW_SWT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int sprd_efuse_raw_prog(struct sprd_efuse *efuse, u32 blk, bool doub,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bool lock, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * We need set the correct magic number before writing the efuse to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * allow programming, and block other programming until we clear the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * magic number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) writel(SPRD_EFUSE_MAGIC_NUMBER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) efuse->base + SPRD_EFUSE_MAGIC_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * Power on the efuse, enable programme and enable double data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * if asked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) sprd_efuse_set_prog_power(efuse, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) sprd_efuse_set_prog_en(efuse, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) sprd_efuse_set_data_double(efuse, doub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Enable the auto-check function to validate if the programming is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sprd_efuse_set_auto_check(efuse, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel(*data, efuse->base + SPRD_EFUSE_MEM(blk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Disable auto-check and data double after programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) sprd_efuse_set_auto_check(efuse, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) sprd_efuse_set_data_double(efuse, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Check the efuse error status, if the programming is successful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * we should lock this efuse block to avoid programming again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) status = readl(efuse->base + SPRD_EFUSE_ERR_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_err(efuse->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "write error status %d of block %d\n", ret, blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel(SPRD_EFUSE_ERR_CLR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) efuse->base + SPRD_EFUSE_ERR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } else if (lock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) sprd_efuse_set_prog_lock(efuse, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel(0, efuse->base + SPRD_EFUSE_MEM(blk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sprd_efuse_set_prog_lock(efuse, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) sprd_efuse_set_prog_power(efuse, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel(0, efuse->base + SPRD_EFUSE_MAGIC_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int sprd_efuse_raw_read(struct sprd_efuse *efuse, int blk, u32 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) bool doub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Need power on the efuse before reading data from efuse, and will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * power off the efuse after reading process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) sprd_efuse_set_read_power(efuse, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Enable double data if asked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) sprd_efuse_set_data_double(efuse, doub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Start to read data from efuse block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *val = readl(efuse->base + SPRD_EFUSE_MEM(blk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Disable double data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sprd_efuse_set_data_double(efuse, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Power off the efuse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sprd_efuse_set_read_power(efuse, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Check the efuse error status and clear them if there are some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * errors occurred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) status = readl(efuse->base + SPRD_EFUSE_ERR_FLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err(efuse->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "read error status %d of block %d\n", status, blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel(SPRD_EFUSE_ERR_CLR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) efuse->base + SPRD_EFUSE_ERR_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int sprd_efuse_read(void *context, u32 offset, void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct sprd_efuse *efuse = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bool blk_double = efuse->data->blk_double;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 index = offset / SPRD_EFUSE_BLOCK_WIDTH + efuse->data->blk_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 blk_offset = (offset % SPRD_EFUSE_BLOCK_WIDTH) * BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = sprd_efuse_lock(efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = clk_prepare_enable(efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = sprd_efuse_raw_read(efuse, index, &data, blk_double);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) data >>= blk_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) memcpy(val, &data, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) clk_disable_unprepare(efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) sprd_efuse_unlock(efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int sprd_efuse_write(void *context, u32 offset, void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct sprd_efuse *efuse = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bool blk_double = efuse->data->blk_double;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) bool lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = sprd_efuse_lock(efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ret = clk_prepare_enable(efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * If the writing bytes are equal with the block width, which means the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * whole block will be programmed. For this case, we should not allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * this block to be programmed again by locking this block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * If the block was programmed partially, we should allow this block to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * be programmed again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (bytes < SPRD_EFUSE_BLOCK_WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) lock = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) lock = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = sprd_efuse_raw_prog(efuse, offset, blk_double, lock, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) clk_disable_unprepare(efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) sprd_efuse_unlock(efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int sprd_efuse_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct nvmem_config econfig = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct sprd_efuse *efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) const struct sprd_efuse_variant_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_err(&pdev->dev, "No matching driver data found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) efuse->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (IS_ERR(efuse->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return PTR_ERR(efuse->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = of_hwspin_lock_get_id(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_err(&pdev->dev, "failed to get hwlock id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) efuse->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!efuse->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(&pdev->dev, "failed to request hwlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) efuse->clk = devm_clk_get(&pdev->dev, "enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (IS_ERR(efuse->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_err(&pdev->dev, "failed to get enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return PTR_ERR(efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mutex_init(&efuse->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) efuse->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) efuse->data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) econfig.stride = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) econfig.word_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) econfig.read_only = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) econfig.name = "sprd-efuse";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) econfig.size = efuse->data->blk_nums * SPRD_EFUSE_BLOCK_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) econfig.reg_read = sprd_efuse_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) econfig.reg_write = sprd_efuse_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) econfig.priv = efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) econfig.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) nvmem = devm_nvmem_register(&pdev->dev, &econfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (IS_ERR(nvmem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_err(&pdev->dev, "failed to register nvmem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return PTR_ERR(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct of_device_id sprd_efuse_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { .compatible = "sprd,ums312-efuse", .data = &ums312_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct platform_driver sprd_efuse_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .probe = sprd_efuse_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .name = "sprd-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .of_match_table = sprd_efuse_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) module_platform_driver(sprd_efuse_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MODULE_DESCRIPTION("Spreadtrum AP efuse driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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