^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2018 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/hwspinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* PMIC global registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SC27XX_MODULE_EN 0xc08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SC2730_MODULE_EN 0x1808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SC27XX_EFUSE_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Efuse controller registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SC27XX_EFUSE_GLB_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SC27XX_EFUSE_DATA_RD 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SC27XX_EFUSE_DATA_WR 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SC27XX_EFUSE_BLOCK_INDEX 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SC27XX_EFUSE_MODE_CTRL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SC27XX_EFUSE_STATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SC27XX_EFUSE_WR_TIMING_CTRL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SC27XX_EFUSE_RD_TIMING_CTRL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SC27XX_EFUSE_EFUSE_DEB_CTRL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Mask definition for SC27XX_EFUSE_BLOCK_INDEX register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SC27XX_EFUSE_BLOCK_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Bits definitions for SC27XX_EFUSE_MODE_CTRL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SC27XX_EFUSE_PG_START BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SC27XX_EFUSE_RD_START BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SC27XX_EFUSE_CLR_RDDONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Bits definitions for SC27XX_EFUSE_STATUS register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SC27XX_EFUSE_PGM_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC27XX_EFUSE_READ_BUSY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SC27XX_EFUSE_STANDBY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SC27XX_EFUSE_GLOBAL_PROT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SC27XX_EFUSE_RD_DONE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Block number and block width (bytes) definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SC27XX_EFUSE_BLOCK_MAX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SC27XX_EFUSE_BLOCK_WIDTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Timeout (ms) for the trylock of hardware spinlocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC27XX_EFUSE_HWLOCK_TIMEOUT 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Timeout (us) of polling the status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC27XX_EFUSE_POLL_TIMEOUT 3000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC27XX_EFUSE_POLL_DELAY_US 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Since different PMICs of SC27xx series can have different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * address , we should save address in the device data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct sc27xx_efuse_variant_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 module_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct sc27xx_efuse {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct hwspinlock *hwlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const struct sc27xx_efuse_variant_data *var_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct sc27xx_efuse_variant_data sc2731_edata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .module_en = SC27XX_MODULE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct sc27xx_efuse_variant_data sc2730_edata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .module_en = SC2730_MODULE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * On Spreadtrum platform, we have multi-subsystems will access the unique
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * efuse controller, so we need one hardware spinlock to synchronize between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * the multiple subsystems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int sc27xx_efuse_lock(struct sc27xx_efuse *efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mutex_lock(&efuse->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ret = hwspin_lock_timeout_raw(efuse->hwlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SC27XX_EFUSE_HWLOCK_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_err(efuse->dev, "timeout to get the hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mutex_unlock(&efuse->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void sc27xx_efuse_unlock(struct sc27xx_efuse *efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) hwspin_unlock_raw(efuse->hwlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mutex_unlock(&efuse->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int sc27xx_efuse_poll_status(struct sc27xx_efuse *efuse, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = regmap_read_poll_timeout(efuse->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) efuse->base + SC27XX_EFUSE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val, (val & bits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SC27XX_EFUSE_POLL_DELAY_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SC27XX_EFUSE_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_err(efuse->dev, "timeout to update the efuse status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int sc27xx_efuse_read(void *context, u32 offset, void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct sc27xx_efuse *efuse = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 buf, blk_index = offset / SC27XX_EFUSE_BLOCK_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 blk_offset = (offset % SC27XX_EFUSE_BLOCK_WIDTH) * BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (blk_index > SC27XX_EFUSE_BLOCK_MAX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bytes > SC27XX_EFUSE_BLOCK_WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ret = sc27xx_efuse_lock(efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Enable the efuse controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ret = regmap_update_bits(efuse->regmap, efuse->var_data->module_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SC27XX_EFUSE_EN, SC27XX_EFUSE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) goto unlock_efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Before reading, we should ensure the efuse controller is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * standby state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = sc27xx_efuse_poll_status(efuse, SC27XX_EFUSE_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) goto disable_efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Set the block address to be read. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = regmap_write(efuse->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) efuse->base + SC27XX_EFUSE_BLOCK_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) blk_index & SC27XX_EFUSE_BLOCK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) goto disable_efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Start reading process from efuse memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = regmap_update_bits(efuse->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) efuse->base + SC27XX_EFUSE_MODE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SC27XX_EFUSE_RD_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SC27XX_EFUSE_RD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto disable_efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Polling the read done status to make sure the reading process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * is completed, that means the data can be read out now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = sc27xx_efuse_poll_status(efuse, SC27XX_EFUSE_RD_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto disable_efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Read data from efuse memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = regmap_read(efuse->regmap, efuse->base + SC27XX_EFUSE_DATA_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) goto disable_efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Clear the read done flag. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = regmap_update_bits(efuse->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) efuse->base + SC27XX_EFUSE_MODE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SC27XX_EFUSE_CLR_RDDONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SC27XX_EFUSE_CLR_RDDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) disable_efuse:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Disable the efuse controller after reading. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) regmap_update_bits(efuse->regmap, efuse->var_data->module_en, SC27XX_EFUSE_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unlock_efuse:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) sc27xx_efuse_unlock(efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) buf >>= blk_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) memcpy(val, &buf, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int sc27xx_efuse_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct nvmem_config econfig = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct sc27xx_efuse *efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) efuse->regmap = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (!efuse->regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) dev_err(&pdev->dev, "failed to get efuse regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = of_property_read_u32(np, "reg", &efuse->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(&pdev->dev, "failed to get efuse base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = of_hwspin_lock_get_id(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(&pdev->dev, "failed to get hwspinlock id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) efuse->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!efuse->hwlock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(&pdev->dev, "failed to request hwspinlock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mutex_init(&efuse->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) efuse->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) efuse->var_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) econfig.stride = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) econfig.word_size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) econfig.read_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) econfig.name = "sc27xx-efuse";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) econfig.size = SC27XX_EFUSE_BLOCK_MAX * SC27XX_EFUSE_BLOCK_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) econfig.reg_read = sc27xx_efuse_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) econfig.priv = efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) econfig.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) nvmem = devm_nvmem_register(&pdev->dev, &econfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (IS_ERR(nvmem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_err(&pdev->dev, "failed to register nvmem config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return PTR_ERR(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct of_device_id sc27xx_efuse_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { .compatible = "sprd,sc2731-efuse", .data = &sc2731_edata},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { .compatible = "sprd,sc2730-efuse", .data = &sc2730_edata},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct platform_driver sc27xx_efuse_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .probe = sc27xx_efuse_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .name = "sc27xx-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .of_match_table = sc27xx_efuse_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) module_platform_driver(sc27xx_efuse_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MODULE_DESCRIPTION("Spreadtrum SC27xx efuse driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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