^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip OTP Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Finley Xiao <finley.xiao@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/rockchip/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* OTP Register Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OTPC_SBPI_CTRL 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OTPC_SBPI_CMD_VALID_PRE 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OTPC_SBPI_CS_VALID_PRE 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OTPC_SBPI_STATUS 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OTPC_USER_CTRL 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OTPC_USER_ADDR 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OTPC_USER_ENABLE 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OTPC_USER_QP 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OTPC_USER_Q 0x0124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OTPC_INT_STATUS 0x0304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OTPC_SBPI_CMD0_OFFSET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OTPC_SBPI_CMD1_OFFSET 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OTPC_MODE_CTRL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OTPC_IRQ_ST 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OTPC_ACCESS_ADDR 0x200c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OTPC_RD_DATA 0x2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OTPC_REPR_RD_TRANS_NUM 0x2020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OTPC_DEEP_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OTPC_STANDBY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OTPC_ACTIVE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OTPC_READ_ACCESS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OTPC_TRANS_NUM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OTPC_RDM_IRQ_ST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OTPC_STB2ACT_IRQ_ST BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OTPC_DP2STB_IRQ_ST BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OTPC_ACT2STB_IRQ_ST BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OTPC_STB2DP_IRQ_ST BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PX30S_NBYTES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PX30S_NO_SECURE_OFFSET 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* OTP Register bits and masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OTPC_USER_ADDR_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OTPC_USE_USER BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OTPC_USE_USER_MASK GENMASK(16, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OTPC_USER_FSM_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OTPC_USER_FSM_ENABLE_MASK GENMASK(16, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OTPC_SBPI_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OTPC_USER_DONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SBPI_DAP_ADDR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SBPI_DAP_ADDR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SBPI_DAP_ADDR_MASK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SBPI_CMD_VALID_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SBPI_DAP_CMD_WRF 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SBPI_DAP_REG_ECC 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SBPI_ECC_ENABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SBPI_ECC_DISABLE 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SBPI_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SBPI_ENABLE_MASK GENMASK(16, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OTPC_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OTPC_TIMEOUT_PROG 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RK3568_NBYTES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RK3588_OTPC_AUTO_CTRL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RK3588_OTPC_AUTO_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RK3588_OTPC_INT_ST 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RK3588_OTPC_DOUT0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RK3588_NO_SECURE_OFFSET 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RK3588_NBYTES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RK3588_BURST_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define RK3588_BURST_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RK3588_ADDR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RK3588_AUTO_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RK3588_RD_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define RV1126_OTP_NVM_CEB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RV1126_OTP_NVM_RSTB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RV1126_OTP_NVM_ST 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RV1126_OTP_NVM_RADDR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RV1126_OTP_NVM_RSTART 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RV1126_OTP_NVM_RDATA 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RV1126_OTP_NVM_TRWH 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RV1126_OTP_READ_ST 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RV1126_OTP_NVM_PRADDR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RV1126_OTP_NVM_PRLEN 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RV1126_OTP_NVM_PRDATA 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RV1126_OTP_NVM_FAILTIME 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RV1126_OTP_NVM_PRSTART 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RV1126_OTP_NVM_PRSTATE 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * +----------+------------------+--------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * | TYPE | RANGE(byte) | NOTE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * +----------+------------------+--------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * | system | 0x000 ~ 0x0ff | system info, read only |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * +----------+------------------+--------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * | oem | 0x100 ~ 0x1ef | for customized |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * +----------+------------------+--------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * | reserved | 0x1f0 ~ 0x1f7 | future extension |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * +----------+------------------+--------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * | wp | 0x1f8 ~ 0x1ff | write protection for oem |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * +----------+------------------+--------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * +-----+ +------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * | wp | -- | wp for oem range |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * +-----+ +------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * | 1f8 | | 0x100 ~ 0x11f |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * +-----+ +------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * | 1f9 | | 0x120 ~ 0x13f |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * +-----+ +------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * | 1fa | | 0x140 ~ 0x15f |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * +-----+ +------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * | 1fb | | 0x160 ~ 0x17f |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * +-----+ +------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * | 1fc | | 0x180 ~ 0x19f |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * +-----+ +------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * | 1fd | | 0x1a0 ~ 0x1bf |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * +-----+ +------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * | 1fe | | 0x1c0 ~ 0x1df |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * +-----+ +------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * | 1ff | | 0x1e0 ~ 0x1ef |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * +-----+ +------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RV1126_OTP_OEM_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define RV1126_OTP_OEM_SIZE 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RV1126_OTP_WP_OFFSET 0x1f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RV1126_OTP_WP_SIZE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* magic for enable otp write func */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ROCKCHIP_OTP_WR_MAGIC 0x524F434B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* each bit mask 32 bits in OTP NVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ROCKCHIP_OTP_WP_MASK_NBITS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static unsigned int rockchip_otp_wr_magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) module_param(rockchip_otp_wr_magic, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MODULE_PARM_DESC(rockchip_otp_wr_magic, "magic for enable otp write func.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct rockchip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct rockchip_otp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct nvmem_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) const struct rockchip_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DECLARE_BITMAP(wp_mask, ROCKCHIP_OTP_WP_MASK_NBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct rockchip_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const char * const *clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) nvmem_reg_read_t reg_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) nvmem_reg_write_t reg_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int (*init)(struct rockchip_otp *otp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int rockchip_otp_reset(struct rockchip_otp *otp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = reset_control_assert(otp->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_err(otp->dev, "failed to assert otp phy %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = reset_control_deassert(otp->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_err(otp->dev, "failed to deassert otp phy %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int px30_otp_wait_status(struct rockchip_otp *otp, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) (status & flag), 1, OTPC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* clean int status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) writel(flag, otp->base + OTPC_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int px30_otp_ecc_enable(struct rockchip_otp *otp, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel(SBPI_DAP_ADDR_MASK | (SBPI_DAP_ADDR << SBPI_DAP_ADDR_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) otp->base + OTPC_SBPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel(SBPI_CMD_VALID_MASK | 0x1, otp->base + OTPC_SBPI_CMD_VALID_PRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) writel(SBPI_DAP_CMD_WRF | SBPI_DAP_REG_ECC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) otp->base + OTPC_SBPI_CMD0_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel(SBPI_ECC_ENABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) writel(SBPI_ECC_DISABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = px30_otp_wait_status(otp, OTPC_SBPI_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_err(otp->dev, "timeout during ecc_enable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int px30_otp_read(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct rockchip_otp *otp = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(otp->dev, "failed to prepare/enable clks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = rockchip_otp_reset(otp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_err(otp->dev, "failed to reset otp phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = px30_otp_ecc_enable(otp, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) while (bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writel(offset++ | OTPC_USER_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) otp->base + OTPC_USER_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) otp->base + OTPC_USER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = px30_otp_wait_status(otp, OTPC_USER_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_err(otp->dev, "timeout during read setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) goto read_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *buf++ = readb(otp->base + OTPC_USER_Q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) read_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int px30s_otp_wait_status(struct rockchip_otp *otp, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ret = readl_poll_timeout_atomic(otp->base + OTPC_IRQ_ST, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (status & flag), 1, OTPC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* clean int status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) writel(flag, otp->base + OTPC_IRQ_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int px30s_otp_active(struct rockchip_otp *otp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mode = readl(otp->base + OTPC_MODE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case OTPC_DEEP_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel(OTPC_STANDBY, otp->base + OTPC_MODE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = px30s_otp_wait_status(otp, OTPC_DP2STB_IRQ_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(otp->dev, "timeout during wait dp2stb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case OTPC_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) writel(OTPC_ACTIVE, otp->base + OTPC_MODE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = px30s_otp_wait_status(otp, OTPC_STB2ACT_IRQ_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(otp->dev, "timeout during wait stb2act\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int px30s_otp_standby(struct rockchip_otp *otp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mode = readl(otp->base + OTPC_MODE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case OTPC_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) writel(OTPC_STANDBY, otp->base + OTPC_MODE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = px30s_otp_wait_status(otp, OTPC_ACT2STB_IRQ_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(otp->dev, "timeout during wait act2stb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case OTPC_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) writel(OTPC_DEEP_STANDBY, otp->base + OTPC_MODE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = px30s_otp_wait_status(otp, OTPC_STB2DP_IRQ_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_err(otp->dev, "timeout during wait stb2dp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int px30s_otp_read(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct rockchip_otp *otp = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unsigned int addr_start, addr_end, addr_offset, addr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int ret, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 out_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (offset >= otp->data->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (offset + bytes > otp->data->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) bytes = otp->data->size - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_err(otp->dev, "failed to prepare/enable clks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = rockchip_otp_reset(otp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_err(otp->dev, "failed to reset otp phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = px30s_otp_active(otp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) addr_start = rounddown(offset, PX30S_NBYTES) / PX30S_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) addr_end = roundup(offset + bytes, PX30S_NBYTES) / PX30S_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) addr_offset = offset % PX30S_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) addr_len = addr_end - addr_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) addr_start += PX30S_NO_SECURE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) buf = kzalloc(sizeof(*buf) * addr_len * PX30S_NBYTES, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) goto read_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) while (addr_len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) writel(OTPC_TRANS_NUM, otp->base + OTPC_REPR_RD_TRANS_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writel(addr_start++, otp->base + OTPC_ACCESS_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) writel(OTPC_READ_ACCESS, otp->base + OTPC_MODE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = px30s_otp_wait_status(otp, OTPC_RDM_IRQ_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_err(otp->dev, "timeout during wait rd\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) goto read_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) out_value = readl(otp->base + OTPC_RD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) memcpy(&buf[i], &out_value, PX30S_NBYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) i += PX30S_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) memcpy(val, buf + addr_offset, (unsigned int)bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) read_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) px30s_otp_standby(otp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int rk3568_otp_read(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct rockchip_otp *otp = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int addr_start, addr_end, addr_offset, addr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int otp_qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 out_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int ret = 0, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) addr_start = rounddown(offset, RK3568_NBYTES) / RK3568_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) addr_end = roundup(offset + bytes, RK3568_NBYTES) / RK3568_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) addr_offset = offset % RK3568_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) addr_len = addr_end - addr_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) buf = kzalloc(array3_size(addr_len, RK3568_NBYTES, sizeof(*buf)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dev_err(otp->dev, "failed to prepare/enable clks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = rockchip_otp_reset(otp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_err(otp->dev, "failed to reset otp phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = px30_otp_ecc_enable(otp, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) while (addr_len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) writel(addr_start++ | OTPC_USER_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) otp->base + OTPC_USER_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) otp->base + OTPC_USER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = px30_otp_wait_status(otp, OTPC_USER_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(otp->dev, "timeout during read setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) goto read_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) otp_qp = readl(otp->base + OTPC_USER_QP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (((otp_qp & 0xc0) == 0xc0) || (otp_qp & 0x20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(otp->dev, "ecc check error during read setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto read_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) out_value = readl(otp->base + OTPC_USER_Q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) memcpy(&buf[i], &out_value, RK3568_NBYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) i += RK3568_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) memcpy(val, buf + addr_offset, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) read_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int rk3588_otp_wait_status(struct rockchip_otp *otp, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = readl_poll_timeout_atomic(otp->base + RK3588_OTPC_INT_ST, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) (status & flag), 1, OTPC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* clean int status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) writel(flag, otp->base + RK3588_OTPC_INT_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int rk3588_otp_read(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct rockchip_otp *otp = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int addr_start, addr_end, addr_offset, addr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int ret = 0, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 out_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (offset >= otp->data->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (offset + bytes > otp->data->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) bytes = otp->data->size - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) addr_start = rounddown(offset, RK3588_NBYTES) / RK3588_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) addr_end = roundup(offset + bytes, RK3588_NBYTES) / RK3588_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) addr_offset = offset % RK3588_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) addr_len = addr_end - addr_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) addr_start += RK3588_NO_SECURE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) buf = kzalloc(array3_size(addr_len, RK3588_NBYTES, sizeof(*buf)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dev_err(otp->dev, "failed to prepare/enable clks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) while (addr_len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) writel((addr_start << RK3588_ADDR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) (RK3588_BURST_NUM << RK3588_BURST_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) otp->base + RK3588_OTPC_AUTO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = rk3588_otp_wait_status(otp, RK3588_RD_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(otp->dev, "timeout during read setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) goto read_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) out_value = readl(otp->base + RK3588_OTPC_DOUT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) memcpy(&buf[i], &out_value, RK3588_NBYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) i += RK3588_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) addr_start++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) memcpy(val, buf + addr_offset, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) read_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int rv1126_otp_init(struct rockchip_otp *otp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) writel(0x0, otp->base + RV1126_OTP_NVM_CEB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_NVM_ST, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) status & 0x1, 1, OTPC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_err(otp->dev, "timeout during set ceb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) writel(0x1, otp->base + RV1126_OTP_NVM_RSTB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_NVM_ST, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) status & 0x4, 1, OTPC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_err(otp->dev, "timeout during set rstb\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) otp->config->read_only = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int rv1126_otp_read(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct rockchip_otp *otp = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) while (bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) writel(offset++, otp->base + RV1126_OTP_NVM_RADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) writel(0x1, otp->base + RV1126_OTP_NVM_RSTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_READ_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) status, status == 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) OTPC_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_err(otp->dev, "timeout during read setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *buf++ = readb(otp->base + RV1126_OTP_NVM_RDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static int rv1126_otp_prog(struct rockchip_otp *otp, u32 bit_offset, u32 data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 bit_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u32 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) writel(bit_offset, otp->base + RV1126_OTP_NVM_PRADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) writel(bit_len - 1, otp->base + RV1126_OTP_NVM_PRLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) writel(data, otp->base + RV1126_OTP_NVM_PRDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) writel(1, otp->base + RV1126_OTP_NVM_PRSTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Wait max 100 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret = readl_poll_timeout_atomic(otp->base + RV1126_OTP_NVM_PRSTATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) status, status == 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) OTPC_TIMEOUT_PROG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_err(otp->dev, "timeout during prog\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int rv1126_otp_write(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct rockchip_otp *otp = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u8 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u8 val_r, val_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) while (bytes--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = rv1126_otp_read(context, offset, &val_r, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) val_w = *buf & (~val_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ret = rv1126_otp_prog(otp, offset * 8, val_w, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) offset++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static int rv1126_otp_wp(void *context, unsigned int offset, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct rockchip_otp *otp = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) bitmap_set(otp->wp_mask, (offset - RV1126_OTP_OEM_OFFSET) / 4, bytes / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return rv1126_otp_write(context, RV1126_OTP_WP_OFFSET, otp->wp_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) RV1126_OTP_WP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int rv1126_otp_oem_write(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (offset < RV1126_OTP_OEM_OFFSET ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) offset > (RV1126_OTP_OEM_OFFSET + RV1126_OTP_OEM_SIZE - 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) bytes > RV1126_OTP_OEM_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) (offset + bytes) > (RV1126_OTP_OEM_OFFSET + RV1126_OTP_OEM_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!IS_ALIGNED(offset, 4) || !IS_ALIGNED(bytes, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = rv1126_otp_write(context, offset, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ret = rv1126_otp_wp(context, offset, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int rockchip_otp_read(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct rockchip_otp *otp = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mutex_lock(&otp->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (otp->data && otp->data->reg_read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = otp->data->reg_read(context, offset, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) mutex_unlock(&otp->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int rockchip_otp_write(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct rockchip_otp *otp = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mutex_lock(&otp->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (rockchip_otp_wr_magic == ROCKCHIP_OTP_WR_MAGIC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) otp->data && otp->data->reg_write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = otp->data->reg_write(context, offset, val, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) rockchip_otp_wr_magic = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) mutex_unlock(&otp->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static struct nvmem_config otp_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .name = "rockchip-otp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .read_only = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .reg_read = rockchip_otp_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .reg_write = rockchip_otp_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const char * const px30_otp_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) "otp", "apb_pclk", "phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const struct rockchip_data px30_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .size = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .clocks = px30_otp_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .num_clks = ARRAY_SIZE(px30_otp_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .reg_read = px30_otp_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct rockchip_data px30s_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .size = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .clocks = px30_otp_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .num_clks = ARRAY_SIZE(px30_otp_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .reg_read = px30s_otp_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const char * const rk3568_otp_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "usr", "sbpi", "apb", "phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const struct rockchip_data rk3568_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .size = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .clocks = rk3568_otp_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .num_clks = ARRAY_SIZE(rk3568_otp_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .reg_read = rk3568_otp_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const char * const rk3588_otp_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "otpc", "apb", "arb", "phy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static const struct rockchip_data rk3588_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .size = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .clocks = rk3588_otp_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .num_clks = ARRAY_SIZE(rk3588_otp_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .reg_read = rk3588_otp_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const char * const rv1106_otp_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) "usr", "sbpi", "apb", "phy", "arb", "pmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const struct rockchip_data rv1106_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .size = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .clocks = rv1106_otp_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .num_clks = ARRAY_SIZE(rv1106_otp_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .reg_read = rk3568_otp_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const char * const rv1126_otp_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) "otp", "apb_pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static const struct rockchip_data rv1126_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .size = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .clocks = rv1126_otp_clocks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .num_clks = ARRAY_SIZE(rv1126_otp_clocks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .init = rv1126_otp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .reg_read = rv1126_otp_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .reg_write = rv1126_otp_oem_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const struct of_device_id rockchip_otp_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #ifdef CONFIG_CPU_PX30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .compatible = "rockchip,px30-otp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .data = (void *)&px30_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .compatible = "rockchip,px30s-otp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .data = (void *)&px30s_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #ifdef CONFIG_CPU_RK3308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .compatible = "rockchip,rk3308-otp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .data = (void *)&px30_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .compatible = "rockchip,rk3308bs-otp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .data = (void *)&px30s_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #ifdef CONFIG_CPU_RK3568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .compatible = "rockchip,rk3568-otp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .data = (void *)&rk3568_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #ifdef CONFIG_CPU_RK3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .compatible = "rockchip,rk3588-otp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .data = (void *)&rk3588_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #ifdef CONFIG_CPU_RV1106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .compatible = "rockchip,rv1106-otp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .data = (void *)&rv1106_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #ifdef CONFIG_CPU_RV1126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .compatible = "rockchip,rv1126-otp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .data = (void *)&rv1126_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) MODULE_DEVICE_TABLE(of, rockchip_otp_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int rockchip_otp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct rockchip_otp *otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) const struct rockchip_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dev_err(dev, "failed to get match data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (soc_is_px30s() || soc_is_rk3308bs())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) data = &px30s_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (!otp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) mutex_init(&otp->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) otp->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) otp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) otp->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (IS_ERR(otp->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return PTR_ERR(otp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) otp->num_clks = data->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) otp->clks = devm_kcalloc(dev, otp->num_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) sizeof(*otp->clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!otp->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) for (i = 0; i < otp->num_clks; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) otp->clks[i].id = data->clocks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) otp->rst = devm_reset_control_array_get_optional_exclusive(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (IS_ERR(otp->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return PTR_ERR(otp->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) otp->config = &otp_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) otp->config->size = data->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) otp->config->priv = otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) otp->config->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (data->init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ret = data->init(otp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) nvmem = devm_nvmem_register(dev, otp->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return PTR_ERR_OR_ZERO(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static struct platform_driver rockchip_otp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .probe = rockchip_otp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .name = "rockchip-otp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .of_match_table = rockchip_otp_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int __init rockchip_otp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = platform_driver_register(&rockchip_otp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) pr_err("failed to register otp driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static void __exit rockchip_otp_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return platform_driver_unregister(&rockchip_otp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) subsys_initcall(rockchip_otp_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) module_exit(rockchip_otp_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) MODULE_DESCRIPTION("Rockchip OTP driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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