^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * RK628 eFuse Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Weixin Zhou <zwx@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/rk628.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EFUSE_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define T_CSB_P_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define T_PGENB_P_S (15 + 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define T_LOAD_P_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define T_ADDR_P_S (15 + 200 + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define T_STROBE_P_S ((150 + 2000 + 100) / 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define T_CSB_P_L 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define T_PGENB_P_L (15 + 200 + 10 + 200 + 190 + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define T_LOAD_P_L (15 + 200 + 200 + 190 + 10 + 100 + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define T_ADDR_P_L (15 + 200 + 5 + 200 + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define T_STROBE_P_L ((150 + 2000 + 100 + 2000) / 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define T_CSB_R_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define T_PGENB_R_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define T_LOAD_R_S 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define T_ADDR_R_S (15 + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define T_STROBE_R_S ((150 + 100) / 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define T_CSB_R_L 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define T_PGENB_R_L 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define T_LOAD_R_L (15 + 5 + 5 + 10 + 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define T_ADDR_R_L (15 + 10 + 5 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define T_STROBE_R_L ((150 + 100 + 50) / 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define T_CSB_P 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define T_PGENB_P 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define T_LOAD_P 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define T_ADDR_P 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define T_STROBE_P 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define T_CSB_R 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define T_PGENB_R 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define T_LOAD_R 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define T_ADDR_R 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define T_STROBE_R 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EFUSE_REVISION 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RK628_EFUSE_BASE 0xb0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RK628_MOD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RK628_INT_STATUS 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RK628_DOUT 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RK628_AUTO_CTRL 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RK628_USER_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RK628_INT_FINISH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RK628_AUTO_ENB BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RK628_AUTO_RD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RK628_ADDR_ROW 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RK628_ADDR_COL 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RK628_A_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define RK628_A_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RK628_NBYTES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_EFUSE_CTRL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_EFUSE_DOUT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct rk628_efuse_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct gpio_desc *avdd_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int rk628_read(struct regmap *regmap, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct rk628_efuse_chip *efuse = container_of(regmap, struct rk628_efuse_chip, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ret = regmap_read(regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dev_err(efuse->dev, "rk628-efuse:failed to read reg 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int rk628_write(struct regmap *regmap, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct rk628_efuse_chip *efuse = container_of(regmap, struct rk628_efuse_chip, regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = regmap_write(regmap, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_err(efuse->dev, "rk628-efuse:failed to write reg 0x%x\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void rk628_efuse_timing_init(struct rk628_efuse_chip *efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 base = efuse->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* enable auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) rk628_write(efuse->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) rk628_read(efuse->regmap, base + RK628_MOD) & (~RK628_USER_MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) base + RK628_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* setup efuse timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) rk628_write(efuse->regmap, (T_CSB_P_S << 16) | T_CSB_P_L, base + T_CSB_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) rk628_write(efuse->regmap, (T_PGENB_P_S << 16) | T_PGENB_P_L, base + T_PGENB_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rk628_write(efuse->regmap, (T_LOAD_P_S << 16) | T_LOAD_P_L, base + T_LOAD_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) rk628_write(efuse->regmap, (T_ADDR_P_S << 16) | T_ADDR_P_L, base + T_ADDR_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) rk628_write(efuse->regmap, (T_STROBE_P_S << 16) | T_STROBE_P_L, base + T_STROBE_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) rk628_write(efuse->regmap, (T_CSB_R_S << 16) | T_CSB_R_L, base + T_CSB_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) rk628_write(efuse->regmap, (T_PGENB_R_S << 16) | T_PGENB_R_L, base + T_PGENB_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) rk628_write(efuse->regmap, (T_LOAD_R_S << 16) | T_LOAD_R_L, base + T_LOAD_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rk628_write(efuse->regmap, (T_ADDR_R_S << 16) | T_ADDR_R_L, base + T_ADDR_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) rk628_write(efuse->regmap, (T_STROBE_R_S << 16) | T_STROBE_R_L, base + T_STROBE_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void rk628_efuse_timing_deinit(struct rk628_efuse_chip *efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 base = efuse->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* disable auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) rk628_write(efuse->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) rk628_read(efuse->regmap, base + RK628_MOD) | RK628_USER_MODE, base + RK628_MOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* clear efuse timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) rk628_write(efuse->regmap, 0, base + T_CSB_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rk628_write(efuse->regmap, 0, base + T_PGENB_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) rk628_write(efuse->regmap, 0, base + T_LOAD_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rk628_write(efuse->regmap, 0, base + T_ADDR_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) rk628_write(efuse->regmap, 0, base + T_STROBE_P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) rk628_write(efuse->regmap, 0, base + T_CSB_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) rk628_write(efuse->regmap, 0, base + T_PGENB_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) rk628_write(efuse->regmap, 0, base + T_LOAD_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) rk628_write(efuse->regmap, 0, base + T_ADDR_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) rk628_write(efuse->regmap, 0, base + T_STROBE_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int rk628_efuse_read(void *context, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct rk628_efuse_chip *efuse = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int addr_start, addr_end, addr_offset, addr_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 out_value, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret = clk_prepare_enable(efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(efuse->dev, "failed to prepare/enable efuse pclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) addr_start = rounddown(offset, RK628_NBYTES) / RK628_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) addr_end = roundup(offset + bytes, RK628_NBYTES) / RK628_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) addr_offset = offset % RK628_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) addr_len = addr_end - addr_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) buf = kzalloc(sizeof(*buf) * addr_len * RK628_NBYTES, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) goto nomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) rk628_efuse_timing_init(efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) while (addr_len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) rk628_write(efuse->regmap, RK628_AUTO_RD | RK628_AUTO_ENB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ((addr_start++ & RK628_A_MASK) << RK628_A_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) efuse->base + RK628_AUTO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) status = rk628_read(efuse->regmap, efuse->base + RK628_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!(status & RK628_INT_FINISH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) out_value = rk628_read(efuse->regmap, efuse->base + RK628_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rk628_write(efuse->regmap, RK628_INT_FINISH, efuse->base + RK628_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) memcpy(&buf[i], &out_value, RK628_NBYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) i += RK628_NBYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) memcpy(val, buf + addr_offset, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rk628_efuse_timing_deinit(efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) nomem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) clk_disable_unprepare(efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct nvmem_config econfig = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "rk628-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .read_only = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct regmap_range rk628_efuse_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) regmap_reg_range(RK628_EFUSE_BASE, RK628_EFUSE_BASE + EFUSE_REVISION),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct regmap_access_table rk628_efuse_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .yes_ranges = rk628_efuse_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .n_yes_ranges = ARRAY_SIZE(rk628_efuse_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct regmap_config rk628_efuse_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "rk628-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .max_register = RK628_EFUSE_BASE + EFUSE_REVISION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .rd_table = &rk628_efuse_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct of_device_id rk628_efuse_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .compatible = "rockchip,rk628-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MODULE_DEVICE_TABLE(of, rk628_efuse_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int __init rk628_efuse_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct rk628_efuse_chip *efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct rk628 *rk628 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) efuse = devm_kzalloc(&pdev->dev, sizeof(struct rk628_efuse_chip),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) efuse->regmap = devm_regmap_init_i2c(rk628->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) &rk628_efuse_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (IS_ERR(efuse->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = PTR_ERR(efuse->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_err(dev, "failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) efuse->clk = devm_clk_get(&pdev->dev, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (IS_ERR(efuse->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev_err(dev, "failed to get pclk: %ld\n", PTR_ERR(efuse->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return PTR_ERR(efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) efuse->avdd_gpio = devm_gpiod_get_optional(dev, "efuse", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) efuse->base = RK628_EFUSE_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) efuse->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) econfig.size = EFUSE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) econfig.reg_read = (void *)&rk628_efuse_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) econfig.priv = efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) econfig.dev = efuse->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) nvmem = devm_nvmem_register(&econfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (IS_ERR(nvmem))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return PTR_ERR(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) platform_set_drvdata(pdev, nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct platform_driver rk628_efuse_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .probe = rk628_efuse_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .name = "rk628-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .of_match_table = rk628_efuse_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) module_platform_driver(rk628_efuse_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_DESCRIPTION("rk628_efuse driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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