^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Amlogic Meson6, Meson8 and Meson8b eFuse Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MESON_MX_EFUSE_CNTL1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MESON_MX_EFUSE_CNTL1_PD_ENABLE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MESON_MX_EFUSE_CNTL1_AUTO_RD_START BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MESON_MX_EFUSE_CNTL1_BYTE_WR_DATA GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MESON_MX_EFUSE_CNTL1_AUTO_WR_BUSY BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MESON_MX_EFUSE_CNTL1_AUTO_WR_START BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MESON_MX_EFUSE_CNTL1_AUTO_WR_ENABLE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK GENMASK(10, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MESON_MX_EFUSE_CNTL2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MESON_MX_EFUSE_CNTL4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct meson_mx_efuse_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct meson_mx_efuse {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk *core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct nvmem_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 mask, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) data = readl(efuse->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) data &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) data |= (set & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) writel(data, efuse->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) err = clk_prepare_enable(efuse->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* power up the efuse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MESON_MX_EFUSE_CNTL1_PD_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MESON_MX_EFUSE_CNTL4_ENCRYPT_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MESON_MX_EFUSE_CNTL1_PD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MESON_MX_EFUSE_CNTL1_PD_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clk_disable_unprepare(efuse->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int meson_mx_efuse_read_addr(struct meson_mx_efuse *efuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int addr, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* write the address to read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regval = FIELD_PREP(MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MESON_MX_EFUSE_CNTL1_BYTE_ADDR_MASK, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* inform the hardware that we changed the address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MESON_MX_EFUSE_CNTL1_BYTE_ADDR_SET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* start the read process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MESON_MX_EFUSE_CNTL1_AUTO_RD_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MESON_MX_EFUSE_CNTL1_AUTO_RD_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MESON_MX_EFUSE_CNTL1_AUTO_RD_START, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * perform a dummy read to ensure that the HW has the RD_BUSY bit set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * when polling for the status below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) readl(efuse->base + MESON_MX_EFUSE_CNTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) (!(regval & MESON_MX_EFUSE_CNTL1_AUTO_RD_BUSY)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 1, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev_err(efuse->config.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "Timeout while reading efuse address %u\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *value = readl(efuse->base + MESON_MX_EFUSE_CNTL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int meson_mx_efuse_read(void *context, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) void *buf, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct meson_mx_efuse *efuse = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int err, i, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) err = meson_mx_efuse_hw_enable(efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for (i = 0; i < bytes; i += efuse->config.word_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) addr = (offset + i) / efuse->config.word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) err = meson_mx_efuse_read_addr(efuse, addr, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) memcpy(buf + i, &tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) min_t(size_t, bytes - i, efuse->config.word_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MESON_MX_EFUSE_CNTL1_AUTO_RD_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) meson_mx_efuse_hw_disable(efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct meson_mx_efuse_platform_data meson6_efuse_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .name = "meson6-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct meson_mx_efuse_platform_data meson8_efuse_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .name = "meson8-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .word_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct meson_mx_efuse_platform_data meson8b_efuse_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .name = "meson8b-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .word_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct of_device_id meson_mx_efuse_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { .compatible = "amlogic,meson6-efuse", .data = &meson6_efuse_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { .compatible = "amlogic,meson8-efuse", .data = &meson8_efuse_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { .compatible = "amlogic,meson8b-efuse", .data = &meson8b_efuse_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODULE_DEVICE_TABLE(of, meson_mx_efuse_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int meson_mx_efuse_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) const struct meson_mx_efuse_platform_data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct meson_mx_efuse *efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) drvdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) efuse->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (IS_ERR(efuse->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return PTR_ERR(efuse->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) efuse->config.name = devm_kstrdup(&pdev->dev, drvdata->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) efuse->config.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) efuse->config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) efuse->config.priv = efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) efuse->config.stride = drvdata->word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) efuse->config.word_size = drvdata->word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) efuse->config.size = SZ_512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) efuse->config.read_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) efuse->config.reg_read = meson_mx_efuse_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) efuse->core_clk = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (IS_ERR(efuse->core_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(&pdev->dev, "Failed to get core clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return PTR_ERR(efuse->core_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) efuse->nvmem = devm_nvmem_register(&pdev->dev, &efuse->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return PTR_ERR_OR_ZERO(efuse->nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct platform_driver meson_mx_efuse_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .probe = meson_mx_efuse_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .name = "meson-mx-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .of_match_table = meson_mx_efuse_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) module_platform_driver(meson_mx_efuse_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MODULE_DESCRIPTION("Amlogic Meson MX eFuse NVMEM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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