^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * NXP LPC18xx/LPC43xx EEPROM memory NVMEM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 Ariel D'Alessandro <ariel@vanguardiasur.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LPC18XX_EEPROM_AUTOPROG 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LPC18XX_EEPROM_AUTOPROG_WORD 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPC18XX_EEPROM_CLKDIV 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LPC18XX_EEPROM_PWRDWN 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LPC18XX_EEPROM_PWRDWN_NO 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LPC18XX_EEPROM_PWRDWN_YES 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LPC18XX_EEPROM_INTSTAT 0xfe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPC18XX_EEPROM_INTSTAT_END_OF_PROG BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPC18XX_EEPROM_INTSTATCLR 0xfe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Fixed page size (bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPC18XX_EEPROM_PAGE_SIZE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* EEPROM device requires a ~1500 kHz clock (min 800 kHz, max 1600 kHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LPC18XX_EEPROM_CLOCK_HZ 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* EEPROM requires 3 ms of erase/program time between each writing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPC18XX_EEPROM_PROGRAM_TIME 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct lpc18xx_eeprom_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) void __iomem *mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned reg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned val_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline void lpc18xx_eeprom_writel(struct lpc18xx_eeprom_dev *eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) writel(val, eeprom->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline u32 lpc18xx_eeprom_readl(struct lpc18xx_eeprom_dev *eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return readl(eeprom->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int lpc18xx_eeprom_busywait_until_prog(struct lpc18xx_eeprom_dev *eeprom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Wait until EEPROM program operation has finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) end = jiffies + msecs_to_jiffies(LPC18XX_EEPROM_PROGRAM_TIME * 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) while (time_is_after_jiffies(end)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val = lpc18xx_eeprom_readl(eeprom, LPC18XX_EEPROM_INTSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (val & LPC18XX_EEPROM_INTSTAT_END_OF_PROG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_INTSTATCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) LPC18XX_EEPROM_INTSTATCLR_PROG_CLR_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) usleep_range(LPC18XX_EEPROM_PROGRAM_TIME * USEC_PER_MSEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (LPC18XX_EEPROM_PROGRAM_TIME + 1) * USEC_PER_MSEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int lpc18xx_eeprom_gather_write(void *context, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct lpc18xx_eeprom_dev *eeprom = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int offset = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * The last page contains the EEPROM initialization data and is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * writable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if ((reg > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (reg + bytes > eeprom->size - LPC18XX_EEPROM_PAGE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) LPC18XX_EEPROM_PWRDWN_NO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Wait 100 us while the EEPROM wakes up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) while (bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(*(u32 *)val, eeprom->mem_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = lpc18xx_eeprom_busywait_until_prog(eeprom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) bytes -= eeprom->val_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) val += eeprom->val_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) offset += eeprom->val_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) LPC18XX_EEPROM_PWRDWN_YES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int lpc18xx_eeprom_read(void *context, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct lpc18xx_eeprom_dev *eeprom = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) LPC18XX_EEPROM_PWRDWN_NO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Wait 100 us while the EEPROM wakes up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) while (bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *(u32 *)val = readl(eeprom->mem_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bytes -= eeprom->val_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val += eeprom->val_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) offset += eeprom->val_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) LPC18XX_EEPROM_PWRDWN_YES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct nvmem_config lpc18xx_nvmem_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .name = "lpc18xx-eeprom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .word_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .reg_read = lpc18xx_eeprom_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .reg_write = lpc18xx_eeprom_gather_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int lpc18xx_eeprom_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct lpc18xx_eeprom_dev *eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) eeprom = devm_kzalloc(dev, sizeof(*eeprom), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!eeprom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) eeprom->reg_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (IS_ERR(eeprom->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return PTR_ERR(eeprom->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) eeprom->mem_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (IS_ERR(eeprom->mem_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return PTR_ERR(eeprom->mem_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) eeprom->clk = devm_clk_get(&pdev->dev, "eeprom");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (IS_ERR(eeprom->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_err(&pdev->dev, "failed to get eeprom clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return PTR_ERR(eeprom->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = clk_prepare_enable(eeprom->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dev_err(dev, "failed to prepare/enable eeprom clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) rst = devm_reset_control_get_exclusive(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_err(dev, "failed to get reset: %ld\n", PTR_ERR(rst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = PTR_ERR(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = reset_control_assert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_err(dev, "failed to assert reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) eeprom->val_bytes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) eeprom->reg_bytes = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Clock rate is generated by dividing the system bus clock by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * division factor, contained in the divider register (minus 1 encoded).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk_rate = clk_get_rate(eeprom->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) clk_rate = DIV_ROUND_UP(clk_rate, LPC18XX_EEPROM_CLOCK_HZ) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_CLKDIV, clk_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Writing a single word to the page will start the erase/program cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_AUTOPROG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) LPC18XX_EEPROM_AUTOPROG_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) lpc18xx_eeprom_writel(eeprom, LPC18XX_EEPROM_PWRDWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) LPC18XX_EEPROM_PWRDWN_YES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) eeprom->size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) lpc18xx_nvmem_config.size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) lpc18xx_nvmem_config.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) lpc18xx_nvmem_config.priv = eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) eeprom->nvmem = devm_nvmem_register(dev, &lpc18xx_nvmem_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (IS_ERR(eeprom->nvmem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = PTR_ERR(eeprom->nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) platform_set_drvdata(pdev, eeprom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) clk_disable_unprepare(eeprom->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int lpc18xx_eeprom_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct lpc18xx_eeprom_dev *eeprom = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clk_disable_unprepare(eeprom->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct of_device_id lpc18xx_eeprom_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { .compatible = "nxp,lpc1857-eeprom" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_DEVICE_TABLE(of, lpc18xx_eeprom_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct platform_driver lpc18xx_eeprom_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .probe = lpc18xx_eeprom_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .remove = lpc18xx_eeprom_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = "lpc18xx-eeprom",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .of_match_table = lpc18xx_eeprom_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) module_platform_driver(lpc18xx_eeprom_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MODULE_AUTHOR("Ariel D'Alessandro <ariel@vanguardiasur.com.ar>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MODULE_DESCRIPTION("NXP LPC18xx EEPROM memory Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags