Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * JZ4780 EFUSE Memory Support driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2017 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (c) 2020 H. Nikolaus Schaller <hns@goldelico.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Currently supports JZ4780 efuse which has 8K programmable bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Efuse is separated into seven segments as below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * The rom itself is accessed using a 9 bit address line and an 8 word wide bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * which reads/writes based on strobes. The strobe is configured in the config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * register and is based on number of cycles of the bus clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * Driver supports read only as the writes are done in the Factory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define JZ_EFUCTRL		(0x0)	/* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define JZ_EFUCFG		(0x4)	/* Configure Register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define JZ_EFUSTATE		(0x8)	/* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define JZ_EFUDATA(n)		(0xC + (n) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* We read 32 byte chunks to avoid complexity in the driver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define JZ_EFU_READ_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define EFUCTRL_ADDR_MASK	0x3FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define EFUCTRL_ADDR_SHIFT	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define EFUCTRL_LEN_MASK	0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define EFUCTRL_LEN_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define EFUCTRL_PG_EN		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define EFUCTRL_WR_EN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define EFUCTRL_RD_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define EFUCFG_INT_EN		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define EFUCFG_RD_ADJ_MASK	0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define EFUCFG_RD_ADJ_SHIFT	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define EFUCFG_RD_STR_MASK	0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define EFUCFG_RD_STR_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define EFUCFG_WR_ADJ_MASK	0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define EFUCFG_WR_ADJ_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define EFUCFG_WR_STR_MASK	0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define EFUCFG_WR_STR_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define EFUSTATE_WR_DONE	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define EFUSTATE_RD_DONE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct jz4780_efuse {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* main entry point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) static int jz4780_efuse_read(void *context, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			     void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct jz4780_efuse *efuse = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	while (bytes > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		size_t start = offset & ~(JZ_EFU_READ_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		size_t chunk = min(bytes, (start + JZ_EFU_READ_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 				    - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		char buf[JZ_EFU_READ_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		ctrl = (start << EFUCTRL_ADDR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			| ((JZ_EFU_READ_SIZE - 1) << EFUCTRL_LEN_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			| EFUCTRL_RD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		regmap_update_bits(efuse->map, JZ_EFUCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 				   (EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				   (EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				   EFUCTRL_PG_EN | EFUCTRL_WR_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				   EFUCTRL_RD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 				   ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 					       tmp, tmp & EFUSTATE_RD_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 					       1 * MSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 					       50 * MSEC_PER_SEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			dev_err(efuse->dev, "Time out while reading efuse data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 				       buf, JZ_EFU_READ_SIZE / sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		memcpy(val, &buf[offset - start], chunk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		val += chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		offset += chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		bytes -= chunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct nvmem_config jz4780_efuse_nvmem_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.name = "jz4780-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.size = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.word_size = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.reg_read = jz4780_efuse_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct regmap_config jz4780_efuse_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.max_register = JZ_EFUDATA(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void clk_disable_unprepare_helper(void *clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	clk_disable_unprepare(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int jz4780_efuse_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct jz4780_efuse *efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct nvmem_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned long rd_adj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	unsigned long rd_strobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (!efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	efuse->map = devm_regmap_init_mmio(dev, regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 					   &jz4780_efuse_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (IS_ERR(efuse->map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return PTR_ERR(efuse->map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	efuse->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (IS_ERR(efuse->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return PTR_ERR(efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	ret = clk_prepare_enable(efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	ret = devm_add_action_or_reset(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				       clk_disable_unprepare_helper,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				       efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	clk_rate = clk_get_rate(efuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	efuse->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 * rd_adj and rd_strobe are 4 bit values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 * conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 *   bus clk_period * (rd_adj + 1) > 6.5ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 *   bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 *   i.e. rd_adj >= 6.5ns / clk_period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 *   i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	 * constants:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 *   1 / 6.5ns == 153846154 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 *   1 / 35ns == 28571429 Hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	rd_adj = clk_rate / 153846154;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (rd_adj > EFUCFG_RD_ADJ_MASK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	    rd_strobe > EFUCFG_RD_STR_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		dev_err(&pdev->dev, "Cannot set clock configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	regmap_update_bits(efuse->map, JZ_EFUCFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			   (EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			   (EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			   (rd_adj << EFUCFG_RD_ADJ_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			   (rd_strobe << EFUCFG_RD_STR_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	cfg = jz4780_efuse_nvmem_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	cfg.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	cfg.priv = efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	nvmem = devm_nvmem_register(dev, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return PTR_ERR_OR_ZERO(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct of_device_id jz4780_efuse_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	{ .compatible = "ingenic,jz4780-efuse" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct platform_driver jz4780_efuse_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.probe  = jz4780_efuse_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.name = "jz4780-efuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.of_match_table = jz4780_efuse_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) module_platform_driver(jz4780_efuse_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MODULE_AUTHOR("PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MODULE_LICENSE("GPL v2");