^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i.MX6 OCOTP fusebox driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on the barebox ocotp driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2010 Baruch Siach <baruch@tkos.co.il>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Orex Computed Radiography
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Write support based on the fsl_otp driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * OTP Bank0 Word0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX_OCOTP_OFFSET_PER_WORD 0x10 /* Offset between the start addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * of two consecutive OTP words.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX_OCOTP_ADDR_CTRL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX_OCOTP_ADDR_CTRL_SET 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX_OCOTP_ADDR_CTRL_CLR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX_OCOTP_ADDR_TIMING 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX_OCOTP_ADDR_DATA0 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX_OCOTP_ADDR_DATA1 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX_OCOTP_ADDR_DATA2 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX_OCOTP_ADDR_DATA3 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX_OCOTP_BM_CTRL_BUSY 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX_OCOTP_BM_CTRL_ERROR 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX_OCOTP_BM_CTRL_REL_SHADOWS 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX_OCOTP_BM_CTRL_ADDR_8MP 0x000001FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX_OCOTP_BM_CTRL_BUSY_8MP 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX_OCOTP_BM_CTRL_ERROR_8MP 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX_OCOTP_BM_CTRL_DEFAULT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .bm_addr = IMX_OCOTP_BM_CTRL_ADDR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .bm_busy = IMX_OCOTP_BM_CTRL_BUSY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .bm_error = IMX_OCOTP_BM_CTRL_ERROR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX_OCOTP_BM_CTRL_8MP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .bm_addr = IMX_OCOTP_BM_CTRL_ADDR_8MP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .bm_busy = IMX_OCOTP_BM_CTRL_BUSY_8MP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .bm_error = IMX_OCOTP_BM_CTRL_ERROR_8MP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .bm_rel_shadows = IMX_OCOTP_BM_CTRL_REL_SHADOWS_8MP,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TIMING_STROBE_PROG_US 10 /* Min time to blow a fuse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TIMING_STROBE_READ_NS 37 /* Min time before read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TIMING_RELAX_NS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DEF_FSOURCE 1001 /* > 1000 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DEF_STROBE_PROG 10000 /* IPG clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX_OCOTP_WR_UNLOCK 0x3E770000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX_OCOTP_READ_LOCKED_VAL 0xBADABADA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static DEFINE_MUTEX(ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct ocotp_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const struct ocotp_params *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct nvmem_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct ocotp_ctrl_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 bm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 bm_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 bm_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 bm_rel_shadows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct ocotp_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int bank_address_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void (*set_timing)(struct ocotp_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct ocotp_ctrl_reg ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 c, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 bm_ctrl_busy, bm_ctrl_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void __iomem *base = priv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bm_ctrl_busy = priv->params->ctrl.bm_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bm_ctrl_error = priv->params->ctrl.bm_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mask = bm_ctrl_busy | bm_ctrl_error | flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) for (count = 10000; count >= 0; count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) c = readl(base + IMX_OCOTP_ADDR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (!(c & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (count < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* HW_OCOTP_CTRL[ERROR] will be set under the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * - A write is performed to a shadow register during a shadow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * reload (essentially, while HW_OCOTP_CTRL[RELOAD_SHADOWS] is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * set. In addition, the contents of the shadow register shall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * not be updated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * - A write is performed to a shadow register which has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * - A read is performed to from a shadow register which has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * been read locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * - A program is performed to a fuse word which has been locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * - A read is performed to from a fuse word which has been read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * locked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (c & bm_ctrl_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void imx_ocotp_clr_err_if_set(struct ocotp_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 c, bm_ctrl_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void __iomem *base = priv->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bm_ctrl_error = priv->params->ctrl.bm_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) c = readl(base + IMX_OCOTP_ADDR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!(c & bm_ctrl_error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int imx_ocotp_read(void *context, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) void *val, size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct ocotp_priv *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) index = offset >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) count = bytes >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (count > (priv->params->nregs - index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) count = priv->params->nregs - index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mutex_lock(&ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) mutex_unlock(&ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = imx_ocotp_wait_for_busy(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_err(priv->dev, "timeout during read setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto read_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) for (i = index; i < (index + count); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) i * IMX_OCOTP_OFFSET_PER_WORD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* 47.3.1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * For "read locked" registers 0xBADABADA will be returned and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * HW_OCOTP_CTRL[ERROR] will be set. It must be cleared by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * software before any new write, read or reload access can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * issued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) imx_ocotp_clr_err_if_set(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) read_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mutex_unlock(&ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void imx_ocotp_set_imx6_timing(struct ocotp_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long strobe_read, relax, strobe_prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* 47.3.1.3.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Program HW_OCOTP_TIMING[STROBE_PROG] and HW_OCOTP_TIMING[RELAX]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * fields with timing values to match the current frequency of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * ipg_clk. OTP writes will work at maximum bus frequencies as long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * as the HW_OCOTP_TIMING parameters are set correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Note: there are minimum timings required to ensure an OTP fuse burns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * correctly that are independent of the ipg_clk. Those values are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * formally documented anywhere however, working from the minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * timings given in u-boot we can say:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * microseconds feels about right as representative of a minimum time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * to physically burn out a fuse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * performing another read is 37 nanoseconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * timing is not entirely clear the documentation says "This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * count value specifies the time to add to all default timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * parameters other than the Tpgm and Trd. It is given in number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * of ipg_clk periods." where Tpgm and Trd refer to STROBE_PROG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * and STROBE_READ respectively. What the other timing parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * are though, is not specified. Experience shows a zero RELAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * value will mess up a re-load of the shadow registers post OTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * burn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clk_rate = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) strobe_read = DIV_ROUND_UP(clk_rate * TIMING_STROBE_READ_NS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 1000000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) strobe_read += 2 * (relax + 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) strobe_prog = DIV_ROUND_CLOSEST(clk_rate * TIMING_STROBE_PROG_US,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) strobe_prog += 2 * (relax + 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) timing |= strobe_prog & 0x00000FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) timing |= (relax << 12) & 0x0000F000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) timing |= (strobe_read << 16) & 0x003F0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned long clk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u64 fsource, strobe_prog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 timing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * 6.4.3.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) clk_rate = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) NSEC_PER_SEC) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) NSEC_PER_SEC) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) timing = strobe_prog & 0x00000FFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) timing |= (fsource << 12) & 0x000FF000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int imx_ocotp_write(void *context, unsigned int offset, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct ocotp_priv *priv = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 *buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u8 waddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 word = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* allow only writing one complete OTP word at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if ((bytes != priv->config->word_size) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (offset % priv->config->word_size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mutex_lock(&ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mutex_unlock(&ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_err(priv->dev, "failed to prepare/enable ocotp clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Setup the write timing values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) priv->params->set_timing(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* 47.3.1.3.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Check that HW_OCOTP_CTRL[BUSY] and HW_OCOTP_CTRL[ERROR] are clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Overlapped accesses are not supported by the controller. Any pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * write or reload must be completed before a write access can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * requested.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = imx_ocotp_wait_for_busy(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_err(priv->dev, "timeout during timing setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) goto write_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* 47.3.1.3.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Write the requested address to HW_OCOTP_CTRL[ADDR] and program the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * unlock code into HW_OCOTP_CTRL[WR_UNLOCK]. This must be programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * for each write access. The lock code is documented in the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * description. Both the unlock code and address can be written in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * same operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (priv->params->bank_address_words != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * In banked/i.MX7 mode the OTP register bank goes into waddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * see i.MX 7Solo Applications Processor Reference Manual, Rev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * 0.1 section 6.4.3.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) offset = offset / priv->config->word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) waddr = offset / priv->params->bank_address_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) word = offset & (priv->params->bank_address_words - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Non-banked i.MX6 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * OTP write/read address specifies one of 128 word address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * locations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) waddr = offset / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ctrl &= ~priv->params->ctrl.bm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ctrl |= waddr & priv->params->ctrl.bm_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ctrl |= IMX_OCOTP_WR_UNLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* 47.3.1.3.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Write the data to the HW_OCOTP_DATA register. This will automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * set HW_OCOTP_CTRL[BUSY] and clear HW_OCOTP_CTRL[WR_UNLOCK]. To
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * protect programming same OTP bit twice, before program OCOTP will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * automatically read fuse value in OTP and use read value to mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * program data. The controller will use masked program data to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * fields with 1's will result in that OTP bit being programmed. Bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * fields with 0's will be ignored. At the same time that the write is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * accepted, the controller makes an internal copy of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * HW_OCOTP_CTRL[ADDR] which cannot be updated until the next write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * sequence is initiated. This copy guarantees that erroneous writes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * HW_OCOTP_CTRL[ADDR] will not affect an active write operation. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * should also be noted that during the programming HW_OCOTP_DATA will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * shift right (with zero fill). This shifting is required to program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * modified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * Note: on i.MX7 there are four data fields to write for banked write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * with the fuse blowing operation only taking place after data0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * has been written. This is why data0 must always be the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * register written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (priv->params->bank_address_words != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Banked/i.MX7 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) switch (word) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Non-banked i.MX6 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* 47.4.1.4.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Once complete, the controller will clear BUSY. A write request to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * protected or locked region will result in no OTP access and no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * setting of HW_OCOTP_CTRL[BUSY]. In addition HW_OCOTP_CTRL[ERROR] will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * be set. It must be cleared by software before any new write access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * can be issued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = imx_ocotp_wait_for_busy(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (ret == -EPERM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_err(priv->dev, "failed write to locked region");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) imx_ocotp_clr_err_if_set(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev_err(priv->dev, "timeout during data write\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto write_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* 47.3.1.4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * Write Postamble: Due to internal electrical characteristics of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * OTP during writes, all OTP operations following a write must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * the write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* reload all shadow registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writel(priv->params->ctrl.bm_rel_shadows,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) priv->base + IMX_OCOTP_ADDR_CTRL_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = imx_ocotp_wait_for_busy(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) priv->params->ctrl.bm_rel_shadows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_err(priv->dev, "timeout during shadow register reload\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) write_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mutex_unlock(&ocotp_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret < 0 ? ret : bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static struct nvmem_config imx_ocotp_nvmem_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .name = "imx-ocotp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .read_only = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .word_size = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .reg_read = imx_ocotp_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .reg_write = imx_ocotp_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct ocotp_params imx6q_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .nregs = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .bank_address_words = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .set_timing = imx_ocotp_set_imx6_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct ocotp_params imx6sl_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .nregs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .bank_address_words = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .set_timing = imx_ocotp_set_imx6_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const struct ocotp_params imx6sll_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .nregs = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .bank_address_words = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .set_timing = imx_ocotp_set_imx6_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct ocotp_params imx6sx_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .nregs = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .bank_address_words = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .set_timing = imx_ocotp_set_imx6_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct ocotp_params imx6ul_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .nregs = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .bank_address_words = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .set_timing = imx_ocotp_set_imx6_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct ocotp_params imx6ull_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .nregs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .bank_address_words = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .set_timing = imx_ocotp_set_imx6_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct ocotp_params imx7d_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .nregs = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .bank_address_words = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .set_timing = imx_ocotp_set_imx7_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct ocotp_params imx7ulp_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .nregs = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .bank_address_words = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const struct ocotp_params imx8mq_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .nregs = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .bank_address_words = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .set_timing = imx_ocotp_set_imx6_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct ocotp_params imx8mm_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .nregs = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .bank_address_words = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .set_timing = imx_ocotp_set_imx6_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const struct ocotp_params imx8mn_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .nregs = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .bank_address_words = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .set_timing = imx_ocotp_set_imx6_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const struct ocotp_params imx8mp_params = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .nregs = 384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .bank_address_words = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .set_timing = imx_ocotp_set_imx6_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .ctrl = IMX_OCOTP_BM_CTRL_8MP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const struct of_device_id imx_ocotp_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { .compatible = "fsl,imx8mp-ocotp", .data = &imx8mp_params },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int imx_ocotp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct ocotp_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) priv->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) priv->params = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) imx_ocotp_nvmem_config.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) imx_ocotp_nvmem_config.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) priv->config = &imx_ocotp_nvmem_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) imx_ocotp_clr_err_if_set(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) nvmem = devm_nvmem_register(dev, &imx_ocotp_nvmem_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return PTR_ERR_OR_ZERO(nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static struct platform_driver imx_ocotp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .probe = imx_ocotp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .name = "imx_ocotp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .of_match_table = imx_ocotp_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) module_platform_driver(imx_ocotp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MODULE_DESCRIPTION("i.MX6/i.MX7 OCOTP fuse box driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags